# Lab 9
Name: Bilwani k
Roll no.: CS22B013

---

## Question 1

module ALU(input [1:0] operand1, // 2-bit input operand 1
           input [1:0] operand2, // 2-bit input operand 2
           input [1:0] control,  // 2-bit control signal
           output reg [1:0] result); // 2-bit output result

   always @(*) begin
      case(control)
         2'b00: result = operand1 + operand2; // Addition
         2'b01: result = operand1 - operand2; // Subtraction
         2'b10: result = operand1 & operand2; // Logical AND
         2'b11: result = operand1 | operand2; // Logical OR
         default: result = 2'b00; // Default case
      endcase
   end

endmodule

module MUX4to1(input [3:0] data, // 4-bit input data
               input [1:0] select, // 2-bit select signal
               output reg out); // Output

   always @(*) begin
      case(select)
         2'b00: out = data[0];
         2'b01: out = data[1];
         2'b10: out = data[2];
         2'b11: out = data[3];
         default: out = 1'b0; // Default case
      endcase
   end

endmodule

module ALU_with_MUX(input [1:0] operand1, // 2-bit input operand 1
                    input [1:0] operand2, // 2-bit input operand 2
                    input [1:0] control, // 2-bit control signal
                    output reg [1:0] result); // 2-bit output result

   wire [1:0] alu_output;
   ALU ALU_inst(.operand1(operand1), .operand2(operand2), .control(control), .result(alu_output));

   wire [3:0] mux_input;
   assign mux_input = {alu_output, 2'b00}; // Concatenate ALU output with 2'b00 for MUX input

   wire [1:0] select_lines;
   assign select_lines = control; // Use control signal as select lines for MUX

   MUX4to1 MUX_inst(.data(mux_input), .select(select_lines), .out(result));

endmodule

---

## Question 2

module simple_processor (
    input [7:0] instruction
);

    // Memory and register declarations
    reg [7:0] memory [255:0]; // 256 bytes of memory
    reg [7:0] reg_file [15:0]; // 16 general-purpose 8-bit registers
    
    // Instruction decoding
    reg [1:0] opcode;
    reg [3:0] src_reg, dest_reg;
    reg [2:0] offset;
    
    // Extracting fields from the instruction
    always @* begin
        opcode = instruction[7:6];
        dest_reg = instruction[5:4];
        offset = instruction[3:1];
        src_reg = instruction[0];
    end
    
    // Load and store operations
    always @* begin
        if (opcode == 2'b00) begin // lw (Load word) operation
            reg_file[dest_reg] = memory[reg_file[src_reg] + offset];
        end
        else if (opcode == 2'b01) begin // sw (Store word) operation
            memory[reg_file[src_reg] + offset] = reg_file[dest_reg];
        end
        // Add more instructions as needed
    end

endmodule

---
## Question 3

#include <stdio.h>

int main() {
    int a = 5;
    int b = 6;
    int c = a + b;
    
    printf("a = %d\n", a);
    printf("b = %d\n", b);
    printf("c = %d\n", c);
    
    return 0;
}