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# System prepended metadata

title: Full-Custom 512-bit SRAM Design Project

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# Full-Custom 512-bit SRAM Design Project  
*45 nm · 6T SRAM · Custom Design*

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This project implements a full-custom 512-bit SRAM in 45 nm, where submodules—including the SRAM 512 bitcell array, WL-enable, precharge, column MUX, write driver, sense amplifier, and power grid—are automatically placed using a SKILL script after manual cell-level layout.
Please turn on subtitles for the explanation.

🎬  Demonstration Link: https://youtu.be/UDpaIkylD78

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# 🔹 1. Top-Level of the Entire Project 
The complete top-level schematic of the 512-bit SRAM macro, including the bitcell array, precharge circuitry, wordline enable, row decoder, column MUX structure, sense amplifier, and write driver.

![image](https://hackmd.io/_uploads/BJcCpXUWbl.png)
![image](https://hackmd.io/_uploads/HyT1nZh-bl.png)


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# 🔹 2. 6T SRAM Bitcell
The fundamental storage element of the SRAM macro, consisting of a cross-coupled inverter pair and two access transistors.

![image](https://hackmd.io/_uploads/HJ8fCmUWZl.png)
![image](https://hackmd.io/_uploads/BkhThbnWWl.png)


**Key Notes**
- Cross-coupled CMOS latch  
- Access transistors controlled by WL  
- BL/BLB interface for read/write  
- Layout supports alternating PG/GP rows  

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# 🔹 3. Precharge & Equalization Circuit
Precharges BL/BLB and equalizes them before every read operation to ensure proper sensing conditions.

![image](https://hackmd.io/_uploads/r1_r07LbZx.png)
![image](https://hackmd.io/_uploads/B1NH3bhWbl.png)


**Key Notes**
- PMOS precharge devices  
- Equalization PMOS transistor between BL/BLB  


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# 🔹 4. Row Decoder
Decodes the 3-bit row address into a one-hot wordline signal and drives the corresponding WL through the WL-enable cell.

![image](https://hackmd.io/_uploads/HkPh0XUb-e.png)
![image](https://hackmd.io/_uploads/HkJi6-2bWl.png)


**Key Notes**
- WL selection  
- Drives high-capacitance WL routing  
- Affects SRAM access time  

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# 🔹 5. Wordline Enable (WL_EN)
Gates each wordline to prevent unnecessary switching and reduce dynamic power.

![image](https://hackmd.io/_uploads/S10OCQIb-l.png)
![image](https://hackmd.io/_uploads/Syjy6b3ZWg.png)

 

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# 🔹 6. Column Decoder (2-to-4 Decoder)
Selects one out of four bitline pairs and operates in coordination with the 4:1 interleaved architecture
![image](https://hackmd.io/_uploads/r1yxkG2Z-x.png)
![image](https://hackmd.io/_uploads/Hk6gJGn-Wg.png)


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# 🔹 7. Column MUX (4-to-1 Interleaving)
Decodes the 2-bit column address into four select signals and drives the corresponding column-mux path for 4-way interleaving.
![image](https://hackmd.io/_uploads/By4l14UZbl.png)
![image](https://hackmd.io/_uploads/ry3SAb2WWe.png)



**Key Notes**
- 4:1 interleaved structure  
- Controlled by column decode logic  

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# 🔹 8. Sense Amplifier
Amplifies the small differential voltage on BL/BLB during read.

![image](https://hackmd.io/_uploads/B1zXJ4L-We.png)
![image](https://hackmd.io/_uploads/BJ5hp-3--l.png)


**Key Notes**
- Converts small ΔV into full logic levels  

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# 🔹 9. Write Driver
Forces BL/BLB to the correct values during write operations.

![image](https://hackmd.io/_uploads/B1iHJ4I-Wl.png)
![image](https://hackmd.io/_uploads/Skra6Z3Z-l.png)


**Key Notes**
- High-drive pull-up/pull-down  
- Overwrites the bitcell  
- Enabled only during write cycles  

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# 🔹 10. Control Logic & Timing Sequencer
Generates all control signals required for precharge, decoding, sensing, and write operations.



**Key Notes**
- Sequencing: Precharge → WL → SA → Read/Write  
- Ensures correct operation under timing constraints  

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# 🔹 11. Read/Write Testbench 

This section documents all control signals—including precharge enable, wordline enable, write enable, sense amplifier enable, and clock—as well as the data input patterns used in SRAM read/write verification, all defined through a custom vector file.

Time steps 0–31 represent the SRAM write phase, while time steps 32–61 correspond to the SRAM read phase using the defined vector file.

![image](https://hackmd.io/_uploads/H1dmbV8-Ze.png)

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# 🔹 12. post-layout simulation

This section presents the waveforms obtained from the post-layout SRAM read/write simulation. The results were generated in Cadence Virtuoso Maestro using the same vector file defined in Section 11.

![image](https://hackmd.io/_uploads/rJrj-48-Wx.png)

# 🔹 13. Power & Energy Summary  

This section summarizes the write, read, and leakage power extracted from simulation using the vector-file–defined time windows.

### Power Results
- **Average Write Power Consumption:** **238.7 μW**  
- **Average Read Power Consumption:** **218.7 μW**  
- **Leakage Power:** **67.93 μW** 
![image](https://hackmd.io/_uploads/By4YfMnZbe.png)


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# 🔹 14. Maximum Frequency Analysis  

The SRAM timing supports a **1 ns clock period**, corresponding to:

$$
f = \frac{1}{1\ \text{ns}} = 1\ \text{GHz}
$$


Thus, the **maximum achievable clock frequency is approximately 1 GHz**.

![image](https://hackmd.io/_uploads/rkwYQfhZbg.png)



# 🔹 Summary of Cells and Functions

| Block | Function | Notes |
|-------|----------|-----------|
| Bitcell | Data storage | 6T static latch |
| Precharge | Precharge BL/BLB | Affects read delay |
| Wordline Enable | Row gating | Reduces dynamic power |
| Row Decoder | One-hot WL select | Drives heavy WL load |
| Column MUX       | Column selection  | 4-way interleaving   |
| Sense Amplifier  | Readout           | Detects small BL/BLB differential voltage with high sensitivity |
| Write Driver     | Write control     | High-drive capability   |
| Control Logic    | Global sequencing | Coordinates clocking, data input, and data output timing      |

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