# Status of research(02/15~02/21)
Prepare for qualification exam
Subject: (1)OS;(2)Probablilty and statistic

# Status of research(02/08~02/14)
## Topic review
Performance optimazation of application on C++
"inline" : In space, it is generally known that the code size of the method using "inline" will be greater than that of using the call function directly.
But that's not always the case. If code size of Fun A is AS, if Fun A be called n times. Relatived repare code size is SS, then overhead of code size is n*SS+AS. Compare to code size of n*AS using inline, if n is larger the same as SS compare to AS. So if SS is larger than AS, using call
Fun A is larger than using inline method.

In time, using memory space is continutely on using inline method. It will reduce probability of page fault. Reduce page fault have berrter
performance than reduce code size.

## Prepare for qualification exam
Subject: (1)OS;(2)Probablilty and statistic

# Status of research(12/28~02/07)
## Coding C# project

PPT link : https://1drv.ms/b/s!AvX3nCJWFIQNgsN57E1TLHqdOiLPgQ?e=K4HrXQ**
video link: https://1drv.ms/u/s!AvX3nCJWFIQNgsN4gsuh7L0pG0yh2Q?e=Pc6b3U

## Prepare for qualification exam
Subject: (1)OS;(2)Probability and statistic

# Status of research(12/21~12/27)
## Paper review:
A WiscKey: Separating Keys from Values in SSD-Conscious Storage
write PaperCritics7
link: https://1drv.ms/b/s!AvX3nCJWFIQNgpsBRRBcXXxY5cTZMw?e=liHVQ4

## Lab3 of emerge memory technology

# Status of research(12/15~12/20)
## Paper present
link: https://1drv.ms/u/s!AvX3nCJWFIQNgo849Or-cj36UzJqLA?e=LftBaU

# Status of research(12/7~12/14)
## Paper review:
1. A Log-Structured Merge Tree-aware Message Authentication Scheme for Persistent Key-Value Stores. 2022

# Status of research(11/16~11/22)
## Paper review:
1. Flash block partitioning for performance optimization
of FTLs using mapping cache, 2012
2. A Superblock-based Flash Translation Layer for NAND
Flash Memory. 2006
## summary:
Paper A
1. Global Translation Table(GTT)
2. Two-level mapping chche : (a) pair-wise fetch; (b) segment-level fetch
3. Good mapping cache management mechanism is important issue.
4. There are two types on flash block, one to save data, the other save
mapping information.They are translation pages (T-pages) and data pages (D-pages) respectively.

=> mapping cache size、T/D-blocks
=> The random workload use pair-wise fetch policy have better performance than others.
=> The seqential workload use segment-level policy is better than others.
=> The overprovision and cache size are key factors of number of T-block.
Paper B
1. The superblock as a set of adjacent logical blocks that share D-blocks
and U-blocks.
2. During garbage collection, we try to separate hot pages from cold pages
and put them into different D-blocks using the hybrid mapping technique.
3. If several adjacent logical blocks share a U-block, the storage
utilization of the U-block will increase.
4. These pages in a block cannot be programmed in random order.
5. PGD is stored in main memory, PMD and PTs are saves in the spare area of NAND flash.
=>The superblock scheme outperforms FAST by reducing the garbage
collection overhead by 32% – 40% over the whole trace.

### Idea:
candiate research direction maybe "workload pattern detection"

### Next week plan:
1. Lab2 on Emerge Memory Tech. class

### Feature plan:
Environmnet setting for test and evaluation after 12/19.

# Status of research(10/20~10/26)
Qualify exam preparation

# status of research(10/12~10/19)
## Paper review
1. Design and Implementation of a New SSD Cache Architecture

Summary:
This paper hopes to modify the kernel, I/O Stack. It allows the kernel to check whether there is data in the SSD. If there is data in the SSD, it will directly access the data from the SSD without going through the FS.
If there is no data in the SSD, then access the HDD through the FS. With this, we can reduce the time of kernel processing I/O requests.

Shortcoming of original design: (a). Overhead of FS; (b) Two times transformation of loacation ; (c) Redundant effort of HDD access.

# Status of research(10/5~10/11)
## Paper review
1. Insider: Designing In-Storage Computing System for Emerging High-Performance Drive(2019)

# Status of research(9/26~10/4)
## Paper review

1.Remap-SSD: Safely and Efficiently Exploiting SSD Address Remapping to Eliminate Duplicate Writes(2021)
2.Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources.(2018)

# Status of research(9/19~9/25)
## Paper review
1、A Rapid Algorithm/Architecture Prototyping Tool for
Solid-State Drive (finial)
## idea
This paper introduce to architecture of standard SSD.l

# Status of research(9/12~9/18)
## Paper review
1、Design Tradeoffs for SSD Performance. (finial)
* [paper](https://github.com/jeffshchen/Paper)
=> (1). Address Mapping design
(2). Garbage Collection
(3). Wear Leveling Strategies

Summary : <a>. Large SSDs, suitably optimized for random read and
write performance
<b>. Workload management:performance is highly workload-
dependent.
<c>. Random write performance and disk lifetime will vary
significantly due to the locality of disk write
operations.
<e>. To average wear leveling in every block.
<f>. The serial interface over which flash
packages receive commands and transmit data
is a primary bottleneck for SSD performance.
<g>. Operational flash parameters:


<h>. The Samsung part takes roughly 100μs to
transfer a 4KB page fromthe on-chip register
to an off-chip controller.
<i>. Interleaving :we can interleave three
operations on the two dies put together. This
would allow both writes and reads to progress
at the speed of the serial interconnect.
<j>. flash packages export an 8-bit wide serial data interface with a similar number of
control pins.
<k>. When a page write is complete, the
previously mapped page location is
superseded since its contents are now out-
of-date.In the worst case, where superseded
pages are distributed evenly across all
blocks, N − 1 cleaning writes
must be issued for every new data write.
<l>. The stable storage representation must allow the recovery algorithm
to determine the most recent instance of a logical page within an allocation pool

2、The DiskSim Simulation Environment Version3_0 ReferenceManual. (Ongoing)
3、Complete Computer System Simulation: The SimOS Approach.(Ongoing)

## Idea
1. Pick up knowedge of Memory/Flash and find out research direction.
2. Research direct to device firmware

## Idea
1. Design of device firmware on SSD.
2. To detailed descript arhitecture of computer storage subsystems.

.paper note
.interesting problems
.possible solution
.random ideas