---
# System prepended metadata

title: HW3&4_Decimal to 7-Seg Display with Reset

---

# HW3&4 Decimal to 7-Seg Display with Reset
---
[TOC]
## 1.實驗目的
此實驗是透過下圖的真值表，做出一個能夠把十進位的數值對應到共陽極七段顯示器的電路，輸入0-9，七段顯示器顯示0-9，輸入10-15，七段顯示器對應為A,b,c,d,E,F，若Reset，七段顯示器顯示H，並使用工作站進行波形模擬
![](https://hackmd.io/_uploads/rkarcNAzT.jpg)
**圖:真值表**
![電路方塊圖.jpg](https://hackmd.io/_uploads/H1oXMUdmT.jpg)
**圖:電路方塊圖**
## 2.RTL與TestBench撰寫
這個電路除了Decimal轉到七段顯示器外，還有一個Reset重置訊號，所以需要透過if-else電路來做出優先權順序，以下為RTL與Testbench的Code.

RTL Code:
```
`timescale 1ns/100ps
module Decimal_to_7SegDisplay (Reset_n,Dec_in,a,b,c,d,e,f,g,dp);

  parameter IN_NUM = 4;

  input   Reset_n;
  input   [IN_NUM-1:0] Dec_in;
  output  a,b,c,d,e,f,g,dp;

  reg [7:0] out_buffer;
  reg     a,b,c,d,e,f,g;

  assign dp = 1'b1;             //Not Present Dop At All Times

  always @(*)
  begin
    if(!Reset_n)                //Reset 7Seg Present H
    begin
      a = 1'b1;
      b = 1'b0;
      c = 1'b0;
      d = 1'b1;
      e = 1'b0;
      f = 1'b0;
      g = 1'b0;
    end

    else
    begin
      case(Dec_in)
        4'd0 :                  //Input:0000 7Seg Present 0
        begin
          a = 1'b0;
          b = 1'b0;
          c = 1'b0;
          d = 1'b0;
          e = 1'b0;
          f = 1'b0;
          g = 1'b1;
        end
        4'd1:                   //Input:0001 7Seg Present 1
        begin
          a = 1'b1;
          b = 1'b0;
          c = 1'b0;
          d = 1'b1;
          e = 1'b1;
          f = 1'b1;
          g = 1'b1;
        end
        4'd2:                   //Input:0010 7Seg Present 2
        begin
          a = 1'b0;
          b = 1'b0;
          c = 1'b1;
          d = 1'b0;
          e = 1'b0;
          f = 1'b1;
          g = 1'b0;
        end
        4'd3:                   //Input:0011 7Seg Present 3
        begin
          a = 1'b0;
          b = 1'b0;
          c = 1'b0;
          d = 1'b0;
          e = 1'b1;
          f = 1'b1;
          g = 1'b0;
        end
        4'd4:                   //Input:0100 7Seg Present 4
        begin
          a = 1'b1;
          b = 1'b0;
          c = 1'b0;
          d = 1'b1;
          e = 1'b1;
          f = 1'b0;
          g = 1'b0;
        end
        4'd5:                   //Input:0101 7Seg Present 5
        begin
          a = 1'b0;
          b = 1'b1;
          c = 1'b0;
          d = 1'b0;
          e = 1'b1;
          f = 1'b0;
          g = 1'b0;
        end
        4'd6:                   //Input:0110 7Seg Present 7
        begin
          a = 1'b0;
          b = 1'b1;
          c = 1'b0;
          d = 1'b0;
          e = 1'b0;
          f = 1'b0;
          g = 1'b0;
        end
        4'd7:                   //Input:0111 7Seg Present 7
        begin
          a = 1'b0;
          b = 1'b0;
          c = 1'b0;
          d = 1'b1;
          e = 1'b1;
          f = 1'b1;
          g = 1'b1;
        end
        4'd8:                   //Input:1000 7Seg Present 8
        begin
          a = 1'b0;
          b = 1'b0;
          c = 1'b0;
          d = 1'b0;
          e = 1'b0;
          f = 1'b0;
          g = 1'b0;
        end
        4'd9:                   //Input:1001 7Seg Present 9
        begin
          a = 1'b0;
          b = 1'b0;
          c = 1'b0;
          d = 1'b0;
          e = 1'b1;
          f = 1'b0;
          g = 1'b0;
        end
        4'd10:                   //Input:1010 7Seg Present A
        begin
          a = 1'b0;
          b = 1'b0;
          c = 1'b0;
          d = 1'b1;
          e = 1'b0;
          f = 1'b0;
          g = 1'b0;
        end
        4'd11:                   //Input:1011 7Seg Present b
        begin
          a = 1'b1;
          b = 1'b1;
          c = 1'b0;
          d = 1'b0;
          e = 1'b0;
          f = 1'b0;
          g = 1'b0;
        end
        4'd12:                   //Input:1100 7Seg Present c
        begin
          a = 1'b1;
          b = 1'b1;
          c = 1'b1;
          d = 1'b0;
          e = 1'b0;
          f = 1'b1;
          g = 1'b0;
        end
        4'd13:                   //Input:1101 7Seg Present d
        begin
          a = 1'b1;
          b = 1'b0;
          c = 1'b0;
          d = 1'b0;
          e = 1'b0;
          f = 1'b1;
          g = 1'b0;
        end
        4'd14:                   //Input:1110 7Seg Present E
        begin
          a = 1'b0;
          b = 1'b1;
          c = 1'b1;
          d = 1'b0;
          e = 1'b0;
          f = 1'b0;
          g = 1'b0;
        end
        4'd15:                   //Input:1111 7Seg Present F
        begin
          a = 1'b0;
          b = 1'b1;
          c = 1'b1;
          d = 1'b1;
          e = 1'b0;
          f = 1'b0;
          g = 1'b0;
        end
      endcase
    end

  end
endmodule

```
Testbench:
```
`timescale 1ns/100ps
module Decimal_to_7SegDisplay_tb;

  parameter NUM_IN = 4;

  reg Reset_n;
  reg [NUM_IN-1:0] Dec_in;
  wire a,b,c,d,e,f,g,dp;

  initial
  begin
    $dumpfile("Decimal_to_7SegDisplay.vcd");
    $dumpvars(0,Dec_to_7Seg);
  end

  integer i;

  initial
  begin
    $monitor("Reset_n = %b, Dec_in = %b, a = %b, b = %b, c = %b, d = %b, e = %b, f = %b, g = %b, dp = %b"
             ,Reset_n,Dec_in,a,b,c,d,e,f,g,dp);

    #0 Reset_n = 1'b0;        //Test Reset
    Dec_in = 4'd5;
    for(i= 0; i<16 ; i=i+1)
    begin
      #10 Reset_n = 1'd1;     //Test Input mapping
      Dec_in = i;
    end
    #10 $finish;
  end

  Decimal_to_7SegDisplay Dec_to_7Seg(
                           .Reset_n(Reset_n),
                           .Dec_in(Dec_in),
                           .a(a),
                           .b(b),
                           .c(c),
                           .d(d),
                           .e(e),
                           .f(f),
                           .g(g),
                           .dp(dp)
                         );
endmodule
```
## 3.FPGA模擬
Schematic圖:
### A.Elaborated Design
![](https://hackmd.io/_uploads/HJ6r-9Rfp.jpg)
**圖: Elaborate Design Layout**
電路圖如同RTL，由MUX決定Reset和輸入的優先權，後進行輸出

### B.Synthesis
![](https://hackmd.io/_uploads/ByvY-qAz6.jpg)
**圖: Synthesis Layout**
Synthesis出來的結果，為利用Buffer和LUT(Look-UP-Table)組成的Combination電路。

### C.Power
![](https://hackmd.io/_uploads/BkW6FVJXT.jpg)
**圖:Power**

## 4.工作站波形模擬
利用工作站來進行波型模擬

A.測試Reset_n，另Reset為0重置電路，並給予輸入，可以發現輸入雖然為5，但仍是執行Reset的結果，輸出1001_0001，如下圖:
![](https://hackmd.io/_uploads/rkZkfQyma.jpg)
**圖4: Reset波型**

B.測試沒有Reset時，波型是否如Truth-Table所設定的值，測試結果如下(拿其中的0,1,2,6,a,e結果來比對)
1.輸入為0000(0)，輸出結果為0000_0011
![](https://hackmd.io/_uploads/SkiGBQy76.jpg)
**圖: Input0000波型**

2.輸入為0001(1)，輸出結果為1001_1111
![](https://hackmd.io/_uploads/BkBjSQJma.jpg)
**圖: Input0001波型**

3.輸入為0010(2)，輸出結果為0010_0101
![](https://hackmd.io/_uploads/Bk_o5QkQp.jpg)
**圖: Input0010波型**

4.輸入為0110(6)，輸出結果為0100_0001
![](https://hackmd.io/_uploads/SyPhZVyX6.jpg)
**圖: Input0110波型**

5.輸入為1010(a)，輸出結果為0001_0001
![](https://hackmd.io/_uploads/Sy8ZfVJ7T.jpg)
**圖: Input1010波型**

6.輸入為1110(e)，輸出結果為0110_0001
![](https://hackmd.io/_uploads/ByRvfVJXT.jpg)
**圖: Input1110波型**

## 5.FPGA開發版模擬
xdc腳位配置為:
左邊的Switch只有用到左邊的那顆，腳位為Reset_n
右邊的四顆Botton由左到右分別為輸入Dec_in的MSB到LSB
輸出由PModA接到共陽極的7段顯示器上

結果討論:
![Reset_n.jpg](https://hackmd.io/_uploads/HkHlXaDmp.jpg)
測試Reset， Reset_n=0, 7Seg=**H**

---
接下來的Reset_n皆=1,由輸入決定輸出
![0.jpg](https://hackmd.io/_uploads/BkwDmav7T.jpg)
a. Dec_in=0000(0), 7Seg=**0**
![1.jpg](https://hackmd.io/_uploads/BkLlE6wX6.jpg)
b. Dec_in=0001(1), 7Seg=**1**
![2.jpg](https://hackmd.io/_uploads/rJGTbAwXT.jpg)
c. Dec_in=0010(2), 7Seg=**2**
![3.jpg](https://hackmd.io/_uploads/H14PMCDXa.jpg)
d. Dec_in=0011(3), 7Seg=**3**
![4.jpg](https://hackmd.io/_uploads/BJ8tfCPX6.jpg)
e. Dec_in=0100(4), 7Seg=**4**
![5.jpg](https://hackmd.io/_uploads/Hk9cG0PX6.jpg)
f. Dec_in=0101(5), 7Seg=**5**
![6.jpg](https://hackmd.io/_uploads/HkA3zADmp.jpg)
g. Dec_in=0110(6), 7Seg=**6**
![7.jpg](https://hackmd.io/_uploads/r1zCM0D7T.jpg)
h. Dec_in=0111(7), 7Seg=**7**
![8.jpg](https://hackmd.io/_uploads/HyhyXCvmp.jpg)
i. Dec_in=1000(8), 7Seg=**8**
![9.jpg](https://hackmd.io/_uploads/SyebmRw7a.jpg)
j. Dec_in=1001(9), 7Seg=**9**
![A.jpg](https://hackmd.io/_uploads/SJY770DQT.jpg)
k. Dec_in=1010(10), 7Seg=**A**
![b.jpg](https://hackmd.io/_uploads/SJZEXAw7a.jpg)
l. Dec_in=1011(11), 7Seg=**b**
![c.jpg](https://hackmd.io/_uploads/S1S4QCvmp.jpg)
m. Dec_in=1100(12), 7Seg=**c**
![d.jpg](https://hackmd.io/_uploads/BkK47CDXp.jpg)
n. Dec_in=1101(13), 7Seg=**d**
![E.jpg](https://hackmd.io/_uploads/r13V7AvmT.jpg)
o. Dec_in=1110(14), 7Seg=**E**
![F.jpg](https://hackmd.io/_uploads/ryJrQ0vmT.jpg)
p. Dec_in=1111(15), 7Seg=**F**

顯示結果皆與真值表相同!

## 6.實驗心得
這次實驗除了RTL設計後到FPGA進行模擬，還使用到了工作站來進行模擬，增加了我們對於工作站的使用經驗，並且把電路燒錄到FPGA開發版上實驗，接到7段顯示器上進行模擬，讓我們對這個電路有更進一步的了解，並解決在開發版模擬時碰到的問題，增加了操作的經驗，以及解決問題的能力。

## 7.參考文獻
SN74L47 datasheet
https://www.ti.com/lit/ds/symlink/sn5447a.pdf?ts=1698189765916&ref_url=https%253A%252F%252Fwww.google.com%252F
漫談七段顯示器
https://www.slideshare.net/ssuser1f4677/ss-78737038