# rocketchip
以下是一個雙核的 rocketCpu SOC
`Each Rocket core is grouped with a page-table walker, L1 instruction cache, and L1 data cache into a RocketTile`
`The Rocket core can also be swapped for a BOOM core. Each tile can also be configured with a RoCC accelerator that connects to the core as a coprocessor`

To customize a RISC-V SoC using the Rocket Chip project, you can modify the relevant configuration files. In this case, if you want to customize the project by removing a specific configuration, such as a 4-core RocketCore, you can make changes accordingly.

The idea is to modify the project's configuration, so that when you execute the "make" command with the desired CONFIG option, the resulting Vivado project in the workspace will reflect your customization. However, it is important to verify if the additional external I/O IPs added to the Vivado project will remain compatible. This concern can be addressed at a later stage.
Coprocessor
PTW(page table walker)這個原始碼不太好懂，閱讀這篇來自 UCB 的文章 [Virtual Memory](https://inst.eecs.berkeley.edu/~cs152/fa16/lectures/L09-VirtualMemory.pdf)
https://chipyard.readthedocs.io/en/1.7.1/Customization/Memory-Hierarchy.html#memory-hierarchy