# Purely handwritten Verilog Risc-V MM-SoC on cheap FPGAs with verification
有些東西先用中文更新...
## datasheet
目標:lite版本可以啟動最基礎的linux，200T版本可以執行片上影像辨識。
CPU部分通過VCS+Verdi仿真後，需要用
### IP & PORTS:
- UART :accept:
- SPI :name_badge:
- ETH:name_badge:
- HDMI:accept:
- CPU(ver 3_stages and ver 5_stages) :accept:
- AXI BUS :name_badge:
### Lite ver & Pro ver platfrom
- Main : GoWin 20K
- Pro : ARTY A7 200T(with out_of_order_SoC)

## [UART](https://github.com/Chiwawachiwawa/NCKUES_MMSoC_Class_UART)(RS232_loop)
I use CH340 to turn USB signals from PC to my UART IP on FPGA.
#### how to solve CDC issue on UART?
let student know more about CDC issues

## HDMI(without audio)
### IP structure
#### HDMI_IP_1280*720_60fps
(you can select colorbar_mode , USB_mode , mipi_mode)

HDMI_TOP structure


HDMI_CTRL_STRUCTURE with TMDS_encoders


- serializer_10_to_1


codes:

module serializer_10_to_1(
    input           paralell_clk,        
    input           serial_clk_5x,       
    input   [9:0]   paralell_data,       
    input           reset,

    output          serial_data          
    );
  
//*****************************************************
//**                    main code
//*****************************************************

OSER10 u_OSER10(
 .Q(serial_data), 
 .D0(paralell_data[0]), 
 .D1(paralell_data[1]),
 .D2(paralell_data[2]), 
 .D3(paralell_data[3]), 
 .D4(paralell_data[4]), 
 .D5(paralell_data[5]),
 .D6(paralell_data[6]), 
 .D7(paralell_data[7]), 
 .D8(paralell_data[8]), 
 .D9(paralell_data[9]), 
 .PCLK(paralell_clk), 
 .FCLK(serial_clk_5x),
 .RESET(reset)
);
defparam u_OSER10.GSREN="false";
defparam u_OSER10.LSREN ="true";

endmodule

- GoWin Primitive codes
example

Verilog 例化：
TLVDS_OBUF uut(
.O(O),
.OB(OB),
.I(I)
);

in my case:
I want to let my 10 bit tmds data turn to

serializer_10_to_1 serializer_clk(
    .paralell_clk       (pclk),                  
    .serial_clk_5x      (pclk_x5),
    .paralell_data      (clk_10bit),
    .reset              (reset),
    .serial_data        (tmds_clk)             
    );

TLVDS_OBUF u_TLVDS_CLK(
    .O  (tmds_clk_p),
    .OB (tmds_clk_n),
    .I  (tmds_clk)
);


### encoderTMDS演算法實現

- driver

this IP support 2 mode if we got a cam data source,we can use this IP to display on monitor,if no,we can just use colorbar_mode.

IP final work:

little tips:why div clock to 5x but 10x?
because serializer_10_to_1 used OSER10,it got some functions like DDR,
that's whywe only div clk to 5x(5*2 = 10)!

## DDR R&W
剛開始想學主要是研究如何透過DDR來跟兩個設備進行資料的交互傳輸，這樣在後期各個 PORT 之間的通信才知道如何處理。
本次實驗採用:
NT5CC128M16JR-EKI
這款型號的晶片，因為ARTY 200T 跟我範例的晶片不同，因此這邊展示的是高雲 FPGA 的實作。
- NCKU_ES_DDR3_RW IP實驗範例:
首先我們來講一下 DDR3 IP 的參數調整(目前用的是高雲的IP)，本次實驗圍繞著高雲自帶的DDR3_interface IP 來進行實作，進行封裝並達到讀寫的功能，為將來的實作所用




PS:高雲似乎換過DDR3的顆粒，導致規格書上的教學有問題，目前先採 xc7a200T 的平台，
NCKUES_DDR3_controller_7A200T IP

## CPU(5 and 2 stage)
#### Risc-V 5-stage CPU
POWER

CPU verdi + VCS 仿真
覆蓋率

## Dual & One port ram
let student know more about CDC issues

## SD card R&W

## SD card BMP reader to HDMI

IP:SPI

EDA tools: