---
# System prepended metadata

title: Lab 9

---

# Lab 9
Name: Lavkush Kumar 
Roll No.: CS22B034

---

## Question 1
**Code** 
```verilog=
module ALU #(parameter DATA_WIDTH=4)(input [DATA_WIDTH-1:0] operand_a,input [DATA_WIDTH-1:0] operand_b,input [1:0] controller,output reg [DATA_WIDTH-1:0] result);

    wire [DATA_WIDTH-1:0] addition_result, subtraction_result, and_result, or_result;

    assign addition_result = operand_a + operand_b;
    assign subtraction_result = operand_a - operand_b;
    assign and_result = operand_a & operand_b;
    assign or_result = operand_a | operand_b;

    always @(*) begin
        case(controller)
            2'b00: result = addition_result;
            2'b01: result = subtraction_result;
            2'b10: result = and_result;
            2'b11: result = or_result;
            default: result = 0; // Default case
        endcase
    end

endmodule

//----------------Test-----------------------//

module ALU_test;
    reg [DATA_WIDTH-1:0] operand_a, operand_b;
    reg [1:0] controller;
    wire [DATA_WIDTH-1:0] result;

    ALU #(4) uut(.operand_a(operand_a),.operand_b(operand_b),.controller(controller),.result(result) );

    initial begin
        operand_a = 4'b0000;
        operand_b = 4'b0000;
        controller = 2'b00;
    end

    always #2 operand_a = operand_a + 1'b1;
    always #1 operand_b = operand_b + 1'b1;
    always #16 controller = controller + 1'b1;

    initial #100 $finish;
endmodule

```
---

## Question 2
**Code** 
```verilog=
module simple_processor(input [7:0] instruction);
    reg [7:0] memory [255:0];
    reg [7:0] reg_file [15:0];
    reg opcode;
    reg [1:0] reg_dest;
    reg [1:0] reg_source;
    reg [2:0] offset;

    reg [7:0] data_out;
    reg [7:0] addr;
    
    always @(*) begin
        opcode = instruction[7];
        reg_dest = instruction[6:5];
        offset = instruction[4:2];
        reg_source = instruction[1:0];
    end
    
    always @(*) begin
        case(opcode)
            1'b0: begin
                memory[addr] = reg_file[reg_source] + offset;
                data_out = memory[addr];
                reg_file[reg_dest] = data_out;
            end
            1'b1: begin
                addr = reg_file[reg_source] + offset;
                memory[addr] = reg_file[reg_dest];
                data_out = 8'b00000000;
            end
            default: begin
                data_out = 8'b00000000;
            end
        endcase
    end
endmodule


```

---

## Question 3

**Code**
```c=
#include<stdio.h>
int main()
{
	int sum =0;
	for(int i=0; i<100; i++)
    {
        sum += i;
    }
	return 0;
}
```
**observation :**
 count value : 116557

---
