---
# System prepended metadata

title: Lab 8

---

# Lab 8
Name: I.Kalyan Anudeep
Roll No.: CS22B025

---
## Question 1
## Full adder using two half adders
**Code** (if required)
```assembly=
module halfadder(
        input a,b,
        output sum,carry
);
assign sum = a^b;
assign carry = a&b;
endmodule

module fulladder(
        input a,b,cin,
        output sum,carry
);
wire s,c,c1;
halfadder HA0(a,b,s,c);
halfadder HA1(cin,s,sum,c1);
assign carry = c | c1;
endmodule


module fulladder_tb;
reg a,b,cin;
wire sum,carry;
fulladder uut(a,b,cin,sum,carry);
initial
begin
        a=0; b=0; cin=0;
        #10
        a=0; b=0; cin=1;
        #10
        a=0; b=1; cin=0;
        #10
        a=0; b=1; cin=1;
        #10
        a=1; b=0; cin=0;
        #10
        a=1; b=0; cin=1;
        #10
        a=1; b=1; cin=0;
        #10
        a=1; b=1; cin=1;
        #10
        $finish();
end
endmodule
```
## Question 2
## 4 bit ripple carry adder
**Code** (if required)
```assembly=
module FullAdder(
        input A,B,cin,
        output sum,cout
);

assign sum=A^B^cin;
assign cout=(A&B)|(cin&(A^B));
endmodule

module Fbitrca(
        input [3:0] A,B,
        input cin,
        output [3:0] Sum,
        output cout
);

        wire c1,c2,c3;
        FullAdder FA0(A[0],B[0],cin,Sum[0],c1);
        FullAdder FA1(A[1],B[1],c1,Sum[1],c2);
        FullAdder FA2(A[2],B[2],c2,Sum[2],c3);
        FullAdder FA3(A[3],B[3],c3,Sum[3],cout);
endmodule

module Fbitrca_tb;
        reg [3:0] A,B,
        reg cin,
        wire [3:0] Sum,
        wire cout
Fbitrca RCA(.A(A),.B(B),.cin(cin),.Sum(Sum),.cout(cout));
initial
begin
    for(int i=0;i<16;i=i+1)begin
        A=i[3:0];
        for(int j=0;j<16;j=j+1)begin
            B=j[3:0];
            for(int k=0;k<2;k=k+1)begin
                cin=k;
            #10
            end
        end
    end
    $finish();
end
endmodule
```

## Question 3
## 2:1 Multiplexer (Structural Modelling)
**Code** (if required)
```assembly=
module mux(
        input a,b,c,
        output o
);
wire w1,w2,w3;
nand(w1,a,c);
nand(w2,c,c);
nand(w3,w2,b);
nand(o,w1,w3);
endmodule

module mux_tb;
reg a,b,c;
wire o;
mux uut(a,b,c,o);
initial
begin
        a=0; b=0; c=0;
        #10
        a=0; b=0; c=1;
        #10
        a=0; b=1; c=0;
        #10
        a=0; b=1; c=1;
        #10
        a=1; b=0; c=0;
        #10
        a=1; b=0; c=1;
        #10
        a=1; b=1; c=0;
        #10
        a=1; b=1; c=1;
        #10
        $finish();
end
endmodule
