# Lab 10 Name: I.Kalyan Anudeep Roll No.: CS22B025 --- ## Question 1 **Code** (if required) ```assembly= module halfadder( input a,b, output sum,carry ); assign sum = a^b; assign carry = a&b; endmodule module fulladder( input a,b,cin, output sum,carry ); wire s,c,c1; halfadder HA0(a,b,s,c); halfadder HA1(cin,s,sum,c1); assign carry = c | c1; endmodule module bitripplecarryadderSubtractor( input [7:0] A,B, input cin,con, output [7:0] Sum, output cout ); wire c1,c2,c3,c4,c5,c6,c7; FullAdder FA0(A[0],B[0]^con,cin,Sum[0],c1); FullAdder FA1(A[1],B[1]^con,c1,Sum[1],c2); FullAdder FA2(A[2],B[2]^con,c2,Sum[2],c3); FullAdder FA3(A[3],B[3]^con,c3,Sum[3],c4); FullAdder FA4(A[4],B[4]^con,cin,Sum[4],c5); FullAdder FA5(A[5],B[5]^con,c1,Sum[5],c6); FullAdder FA6(A[5],B[6]^con,c2,Sum[6],c7); FullAdder FA7(A[7],B[7]^con,c3,Sum[7],cout); endmodule module ripplecarry( input [31:0] a,b, input cin,con, output [31:0] sum, output cout ); wire [7:0] i1,i2,i3,i4,j1,j2,j3,j4,k1,k2,k3,k4; wire c1,c2,c3,c4; assign i1=A[7:0]; assign i2=A[15:8]; assign i3=A[23:16]; assign i4=A[31:24]; assign j1=B[7:0]; assign j2=B[15:8]; assign j3=B[23:16]; assign j4=B[31:24]; bitripplecarryadderSubtractor BS1(i1,j1,cin,con,k1,c1); bitripplecarryadderSubtractor BS2(i2,j2,c1,con,k2,c2); bitripplecarryadderSubtractor BS3(i3,j3,c2,con,k3,c3); bitripplecarryadderSubtractor BS4(i4,j4,c3,con,k4,cout); assign sum={k4,k3,k2,k1}; endmodule module oring( input[7:0] a,b, output[7:0] c ); c[0]=a[0]|b[0]; c[1]=a[1]|b[1]; c[2]=a[2]|b[2]; c[3]=a[3]|b[3]; c[4]=a[4]|b[4]; c[5]=a[5]|b[5]; c[6]=a[6]|b[6]; c[7]=a[7]|b[7]; endmodule module ororing( input[31:0]a,b, output[31:0]c ); wire [7:0] i1,i2,i3,i4,j1,j2,j3,j4,k1,k2,k3,k4; wire c1,c2,c3,c4; assign i1=A[7:0]; assign i2=A[15:8]; assign i3=A[23:16]; assign i4=A[31:24]; assign j1=B[7:0]; assign j2=B[15:8]; assign j3=B[23:16]; assign j4=B[31:24]; oring OR1(i1,j1,k1); oring OR2(i2,j2,k2); oring OR3(i3,j3,k3); oring OR4(i4,j4,k4); assign c={k1,k2,k3,k4}; endmodule module anding( input[7:0] a,b, output[7:0] c ); c[0]=a[0]&b[0]; c[1]=a[1]&b[1]; c[2]=a[2]&b[2]; c[3]=a[3]&b[3]; c[4]=a[4]&b[4]; c[5]=a[5]&b[5]; c[6]=a[6]&b[6]; c[7]=a[7]&b[7]; endmodule module andanding( input[31:0]a,b, output[31:0]c ); wire [7:0] i1,i2,i3,i4,j1,j2,j3,j4,k1,k2,k3,k4; wire c1,c2,c3,c4; assign i1=A[7:0]; assign i2=A[15:8]; assign i3=A[23:16]; assign i4=A[31:24]; assign j1=B[7:0]; assign j2=B[15:8]; assign j3=B[23:16]; assign j4=B[31:24]; anding AND1(i1,j1,k1); anding AND2(i2,j2,k2); anding AND3(i3,j3,k3); anding AND4(i4,j4,k4); assign c={k1,k2,k3,k4}; endmodule module xoring( input[7:0] a,b, output[7:0] c ); c[0]=a[0]^b[0]; c[1]=a[1]^b[1]; c[2]=a[2]^b[2]; c[3]=a[3]^b[3]; c[4]=a[4]^b[4]; c[5]=a[5]^b[5]; c[6]=a[6]^b[6]; c[7]=a[7]^b[7]; endmodule module xorxoring( input[31:0]a,b, output[31:0]c ); wire [7:0] i1,i2,i3,i4,j1,j2,j3,j4,k1,k2,k3,k4; wire c1,c2,c3,c4; assign i1=A[7:0]; assign i2=A[15:8]; assign i3=A[23:16]; assign i4=A[31:24]; assign j1=B[7:0]; assign j2=B[15:8]; assign j3=B[23:16]; assign j4=B[31:24]; xoring XOR1(i1,j1,k1); xoring XOR2(i2,j2,k2); xoring XOR3(i3,j3,k3); xoring XOR4(i4,j4,k4); assign c={k1,k2,k3,k4}; endmodule module ALU(input [31:0] a,b, input cin,cout, input [2:0] c, output reg result[31:0] ); always @(*) begin case(c) 3'b000:ripplecarry(a,b,cin,0,result,cout); 3'b001:ripplecarry(a,b,cin,1,result,cout); 3'b010:xorxoring(a,b,result); 3'b011:andanding(a,b,result); 3'b100:ororing(a,b,result); endcase end endmodule ``` ```c= ``` _You can use either one of these according to the question_ **1 a** Code of ALU implemented above **1 b** Your answer **1 c** Your answer **Observation:** (if required) This is where you will write your observations * Line 1 * Line 2 * Line3 ---