---
# System prepended metadata

title: Introduction to FPGA and Installation

---

# Introduction to FPGA and Installation

[ToC]

# Verilog HDL
## HDL
*[HDL]:Hardware Description Language

Wiki definition [^first]:
>In computer engineering, a `hardware description language (HDL) `is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.
>
The key difference between HDLs and other programming languages are[^second]
- The capability to explicitly `express notion of time`. (defining clocks, delays etc)
- The capability to model `concurrent` threads/process (which is how hardware operates)
- Ability to model at different abstraction - structural/gate level, RTL (Register Transfer Level) or behavioral model

What is the difference between hardware description language HDL and assembly language?[^third]
- VHDL / HDL describes hardware components. It's basically a way of describing the large electronic schematic that is a chip. It "compiles" to a chipmask that you can use `to produce a chip with`.
- Assembly language is the lowest level language that a CPU can actually understand, as each assembly instruction translates to a single machine code instruction.

Reference: 
- [Difference between Hardware Description Language (HDL) and Computer Programming Language C](https://youtu.be/RNuhtjpKVtU)
- [FPGA RTL Design Language Adoption Trends](https://blogs.mentor.com/verificationhorizons/blog/tag/1364/)
## Verilog
Wiki definition[^fourth]:
>Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the `design` and `verification` of digital circuits at the `register-transfer level` of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog is officially part of the SystemVerilog language. The current version is IEEE standard 1800-2017.
>
Reference:
[Verilog Standard Download](https://ieeexplore.ieee.org/document/1620780)

History[^fifth]
- Verilog was developed by Gateway Design Automation as a proprietary language for logic simulation in 1984.
- Gateway was acquired by Cadence in 1989
- Verilog was made an open standard in 1990 under the control of Open Verilog International.
- The language became an IEEE standard in 1995 (IEEE STD 1364) and was updated in 2001 and 2005.
## SystemVerilog
Wiki definition[^sixth]
>SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, `design`, `simulate`, `test` and `implement` electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008 Verilog is now part of the same IEEE standard. It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog.
>
Reference: 
[SystemVerilog Standard Download](https://ieeexplore.ieee.org/document/8299595)

History[^seventh]

- SystemVerilog is the industry's first unified hardware description and verification language
- Started with Superlog language to Accellera in 2002
- Verification functionality (base on OpenVera language) came from Synopsys
- In 2005 SystemVerilog was adopted as IEEE Standard (1800-2005).
# Design Environment
![Imgur](https://i.imgur.com/QJhdreq.png)
Reference:
- [FPGA行业发展情况](http://www.andestech.com/_upload/files/2018%20Andes%20RISC-V%20Con%20Beijing/8_Outlook%20of%20Heterogeneous%20Programmable%20Compute%20Chip.pdf)
- [Field Programmable Gate Array (FPGA) Market Size, Share, Report, Analysis, Trends & Forecast to 2026](https://www.reuters.com/brandfeatures/venture-capital/article?id=31516)
- [Beyond the FPGA: Xilinx’s new CEO talks about what’s next](https://www.datacenterdynamics.com/analysis/beyond-the-fpga-xilinxs-new-ceo-talks-about-whats-next/)

請同學在使用整套開發工具時，務必小心操作，以免造成毀損，一旦毀損請同學照價賠償。目前美金售價請參考下圖（2019.03.28）
[Nexys A7](https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/)
![Imgur](https://i.imgur.com/qbl4fSE.png)
 
常見破壞：USB接頭脫落。此為不可回復的破壞，板子直接報廢。同學在連接USB纜線時，注意角度與力道。
![Imgur](https://i.imgur.com/QlZaBQa.jpg)

## Xilinx Vivado IDE
*[IDE]:Integrated Development Environment

Vivado was introduced in April 2012, and is an integrated design environment (IDE) with system-to-IC level tools built on a shared scalable data model and a common debug environment. Vivado includes electronic system level (ESL) design tools for synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems. A free version WebPACK Edition of Vivado provides designers with a limited version of the design environment which. It will not work when developing for Digilent FPGAs that use a Kintex-7 or Virtex-7 part. 

Vivado is a design environment for FPGA products from Xilinx, and is tightly-coupled to the architecture of such chips, and cannot be used with FPGA products from other vendors.[^eighth]
### Donwload Vivado IDE
1. Create a Xilinx account [here](https://www.xilinx.com/registration/create-account.html) for downloading. 

1. Search keyword "[vivado download](http://lmgtfy.com/?q=vivado+download)" and enter the Xilinx official website.![search](https://i.imgur.com/CVRlfYx.png) ![Imgur](https://i.imgur.com/gxoHti8.png)
1. Enter download page and find `"Vivado Design Suite - HLx Editions"`  according your own PC environment. (Windows or Linux) __DO NOT CHOOSE__ `"Lab Solutions"` which can only perform programming and debugging without generating bitstream file. (Editor comment: current verison:2018.3 on 2019.02.22)![Imgur](https://i.imgur.com/KMIuSus.png)
1. Sign in and save file.![Imgur](https://i.imgur.com/v48adFY.png)![Imgur](https://i.imgur.com/XSBany7.png)
1. Run the installer: __Xilinx_Vivado_SDK_Web_20xx.x_xxxx_xxx_Win64.exe.__
Depending on your Windows security settings, you may get a window asking if you are sure you want to run this program. Answer "Yes".![Imgur](https://i.imgur.com/kTgpHYL.png)
1. Agree the firewall access privilege of Java.![Imgur](https://i.imgur.com/Sdtgi8Z.png)
1. At the Welcome screen, make sure that the operating system of the computer being used is listed in the compatibility list, then click __Next>__.![Imgur](https://i.imgur.com/fp4cqT3.png)
1. Use the same credentials as on the Xilinx website for user authentication. Select the Download and Install Now option and click __Next>__.![Imgur](https://i.imgur.com/hLbndyl.png)
1. Accept all license agreements. Click __Next>__.![Imgur](https://i.imgur.com/OS74zkx.png)
1. Select "__Vivado__". Click __Next>__. ![Imgur](https://i.imgur.com/YkPwKtm.jpg)s


1. Select "__Vivado HL Webpack__" Click __Next>__.![Imgur](https://i.imgur.com/fca9QMV.png)
1. __DO NOT USE__ default software component collections[^nineth] which consume huge disk storage. Customize the installation components. Click __Next>__ ![Imgur](https://i.imgur.com/6b8Wxrs.png)

+ Option detail:
  + Design Tools: 
    + Vivado Design Suite: 
      + Installs the main Vivado development environment. 
    + Software Development Kit:
      + Installs an Eclipse-based development environment for Microblaze and Zynq designs.
    + DocNav: 
      + Installs a navigation tool to quickly find appropriate Xilinx documentation of IP and examples.
  + Devices: 
    + Allows customization of the set of Xilinx FPGA parts that can be designed for after installation.
  + Installation Options:
    + Install Cable Drivers: 
      + Installs the appropriate drivers so that a connected FPGA can be programmed. If Vivado has not been installed before, make sure to check this!
    + Acquire or Manage a License Key: 
      + Launches the Xilinx License manager after installation is complete. Most users do not need to manage licenses.)
12. Set intallation path. __IT WILL CAUSE CRITICAL, UNPREDICTABLE ERRORS__ if path with: non-English characters, initial character with number, space character, etc. It is recommanded to adopt default path under disk C:\Xilinx\. Clcik __Next>__![Imgur](https://i.imgur.com/KcOU0F8.png)
4. Check installation summary. Click __Install__ ![Imgur](https://i.imgur.com/LCUq78y.png)
5. Installing. Wait until the installer has finished installing all components. ![Imgur](https://i.imgur.com/8gbtrzk.png)
6. Permit Device Driver Installation. ![Imgur](https://i.imgur.com/S2QSDKI.png)
7. Permit firewall access again. ![Imgur](https://i.imgur.com/KfNbN8k.png)
8. Complete. Click __OK__. ![Imgur](https://i.imgur.com/wF5jtb1.png)
### ~~Download and~~ import board File of Nexus 4 DDR
~~After installing Vivado, the default installation directory on your drive will contain a folder called board_files. By default this folder contains XML files for different FPGA boards manufactured by Xilinx. XML files define different interfaces on the board. Interfaces such as Slide Switches, Push Buttons, LEDs, USB-UART, DDR Memory, Ethernet etc.~~[^tenth] 
~~1. Search keyword “digilent board files github”.~~
~~2. Access the repository of Digilent.~~
~~3. Click "__Clone or Download__" button and save the zip file.~~
~~4. Uzip the board files.~~
~~5. Find "nexys4_ddr" board files folder. Path:` [Your_download_directory]\vivado-boards-master\new\borad_files`~~
~~6. Navigate to the board_files folder in the Vivado Installation directory (e.g. C:\Xilinx\Vivado\2018.3\data\boards\board_files). Copy "nexys4_ddr" folder to there.~~

1. Execute "Vivado 2020.2" and wait for welcome page.![Imgur](https://i.imgur.com/6JXjmYA.png)
2. Select "XHub Stores" and switch to "Boards" tab.![Imgur](https://i.imgur.com/XWpAld9.png)
3. Expand the menu and find "Nexys4 DDR" item. Right click the item and select "__install...__".![Imgur](https://i.imgur.com/nCobput.png)
4. After a sucessful board file installation, you will see a green tick icon. Now you can close the XHub store window. ![Imgur](https://i.imgur.com/lqJjlSa.png)

## Digilent Nexys 4 DDR  (a.k.a. Digilent Nexys 4 Artix-7 100)
>The Nexys 4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx®. With its large, high-capacity FPGA, generous external memories, and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an `accelerometer`, `temperature sensor`, MEMs digital `microphone`, a `speaker amplifier`, and several I/O devices allow the Nexys 4 DDR to be used for a wide range of designs without needing any other components.[^eleventh]
# Development Cycle
![Imgur](https://i.imgur.com/XZxEtTL.png)
There are several steps required for the development of Xilinx® FPGA RTL when using Xilinx® Vivado IDE.
1. Create a Vivado project. Add and edit the source code files for your circuit design.
2. Debug the circuit using Vivado IDE's software simulator. This will allow you to verify the basic functionality of your code while protecting your design's circuitry in case of any unanticipated malfunctions in your code.
3. When you are sure your code has a reasonable chance of running on hardware and continue to debug your code on an actual FPGA hardware.

# Lecture 0
You will learn:
- How to develop a plan for a FPGA design. 
## Before coding
`Coding` is one of the `last phases` when developing software-based systems. The most common mistake is writing code before completely understanding the problem. Even a simple plan helps to guide the developer to design a system that meets the stated requirements.

 The first step is to have a complete understanding of the requirements or specifications. In other words, state in common human language what it is that the final design will do. Although the life cycle process appears to be a single pass, the final phase often results in cycling through the entire process numerous times to ensure that the delivered system meets the customer’s expectations.

__Life cycle of a software-based system design plan__
Phase|Activity|Output|
|----|--------|------|
|Concept|Understanding the purpose, use, or objectives|Problem statement|
|Requirements|Define specific characteristics and capabilities – what the design will do.|Validated detailed requirements and specifications|
|Design|Describe how the requirements will be met and compliance be measured.|A series of concept, circuit diagrams, plans identifying required resources.|
|Construction|Build hardware components and write software code|A software based system|
|Test|Verify system meets requirements|Test compliance report|
|Evaluation|Evaluation of reliability and functionality|Recommendations for improvements|
## Design example
__Concept__
This example focuses on control of Nexys 4 Artix-7 I/O pins. It consists of a simple example that demonstrates the `syntax`, as well as a mini project. The mini project is designed to demonstrate the process for approaching software-based design of an open-ended problem and to apply the design approach given only the performance specifications.

__Problem Statement__
You will light up a single LED.
# Lecture 1
You will learn:
- How to create a project
- How to control screen layout of Vivado IDE
## A blank design example
__Create a New project__
1. Execute Vivado IDE. At the welcome screen, select `Create Project >`.![Imgur](https://i.imgur.com/jR0j8jq.png)
Or you can use `File >Project > New...`![Imgur](https://i.imgur.com/oznTTQ4.jpg)
2. Project wizard page. Click __Next>__![Imgur](https://i.imgur.com/2iTyDzo.png)
3. Enter "Project name" and select "Project location". __IT WILL CAUSE CRITICAL, UNPREDICTABLE ERRORS__ if path with: non-English characters, initial character with number, space character, etc. It is recommanded to adopt default path under disk C:\/FPGA. Clcik __Next>__![Imgur](https://i.imgur.com/zi2e99m.png)
4. Select `RTL Project` as the Project Type. Clcik __Next>__![Imgur](https://i.imgur.com/lIf9w9y.png)
5. Add a blank RTL code file to the project.![Imgur](https://i.imgur.com/i761PWq.png)After creating, Clcik __Next>__![Imgur](https://i.imgur.com/53MBT2s.png)
6. Skip adding constrains file. Clcik __Next>__![Imgur](https://i.imgur.com/XAKao6P.png)
7. If you have imported the borad files correctly, you can see `Nexys4 DDR` in the hardware list. Clcik __Next>__![Imgur](https://i.imgur.com/UZa02FN.png)
8. Check the project summary. Clcik __Finish__ if all settings are acceptable.![Imgur](https://i.imgur.com/izoYylx.png)
1. Skip module defining wizard. Just click __OK__ and __Yes__.![Imgur](https://i.imgur.com/W8uJVUl.png)

After all previous steps, now you have a project(name: blankDemo) with a blank code file(name: myDemo.v). The file structure is shown in `Sources` window. Double click on __myDemo.v__ in `Sources` window, you can open and edit the content of the file. Editor window is on the right of the IDE screen.![Imgur](https://i.imgur.com/YUtQTPi.png)

These are window control buttons.![Imgur](https://i.imgur.com/2HPNSfO.png)

To save the precious screen area, you could try to rearrange the window layout like this, editor only and keep other function window as tabs(i.e. minimize all other windows).![Imgur](https://i.imgur.com/TZ7xPg9.png)

You can reset all settings to default.![Imgur](https://i.imgur.com/AKlPbgc.png)

# Lecture 2
You will learn:
- Understand a fundemental routine for developing a circuit design
- Start to wirte basic Verilog HDL code
- Familiar with Xilinx Vivado IDE toolchain

Now, focus on code editor window. The default template looks like this:
```verilog=
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 
// Design Name: 
// Module Name: myDemo
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module myDemo(

    );
endmodule

```
The following paragraghs are all about the keywords of Verilog.
## module
__Simplified Syntax__
```
module | macromodule identifier (port_list) ;
    ports_declaration ;
    module_body ;
endmodule
```
All module declarations must `begin with the module` (or macromodule) keyword and `end with the endmodule` keyword. After the module declaration, an identifier is required. A ports list is an option. After that, ports declaration is given with declarations of the direction of ports and the optionally type. The body of module can be any of the following:
- Any declaration including parameter, function, task, event or any variable declaration.
- Continuous assignment.
- Gate or module instantiation.
- Specify block.
- Initial block
- Always block.

If there is no instantiation inside the module, it will be treated as a top-level module
A legit Verilog HDL code snippet.

__Example__
最小符合規格的 Verilog HDL 程式片段。
```Verilog=
module myDemo();
endmodule
```
It must have `module` and `endmodule` pair in a legit module snippet.
程式碼中，`module`與`endmodule`一定是成對出現。

The name of this module is `myDemo` which can be defined by user.
`myDemo()` 為此 module 的名稱，可以自定義。

Although this code pass the process of synthesis, the `myDemo` module with empty design code does nothing here.
`myDemo`模組可以通過`synthesis`階段，但因為缺乏功能設計，所以無法執行任何工作。
___
## comment
__Simplified Syntax__
```
// a single line with comments
/* multiple lines
containing comments */
```
__Example__
Verilog HDL use c-like comment style.
Verilog 註解格式與 c 語言相似。

Make sure you have left approprieate comments for each design.
請為每項設計都留下合適的註解。

```Verilog=
module myCircuitName(// circuit I/O);
    // double slash, single line comments 單行註解
    
    // circuit design description
    // 電路設計描述
        
    /* multiple
       lines
       comments
       多行註解 */
endmodule
```
# Lecture 3

## Goal: Light up an LED
Assume we want to light up an LED on the Nexys 4 Artix-7 board. How should we do to implement this design?

[Video Tutorial](https://youtu.be/EqmkhQ-qqoo)

## Reference design
```Verilog
module myled(
    input mySW, //  a switch to control led
    output myled  // a led to display switch status
    );
    assign myled = mySW;
    
endmodule
```
Your .v editor screen will show like below.
![Imgur](https://i.imgur.com/14ZCxAg.png)

___Remember to save after every work___
Next, start to `Run Synthesis`
![Imgur](https://i.imgur.com/YMERouL.png)

After Synthesis complete, we need generate a .xdc file to tell Vivado how to connect verilog file to a real hardware.
Select `Open Synthesis Design` and click `OK`
![Imgur](https://i.imgur.com/C5jCLcq.png)

When Sythesized Design is ready, your screen should be an `I/O Planning` layout. You can check upper right corner.
![Imgur](https://i.imgur.com/8MDUHq3.png)

Now, focus on the bottom section. There are all ports(i.e. inputs and outputs) found in your verilog design. Left click on `>` symbool next to `Scalar ports(2)` to expand all ports.
Because of different screen resolutions, you may not see all information clearly. Change column width to fit your screen.
![Imgur](https://i.imgur.com/vG6tnbW.png)

In order to connect HDL code with the physical pins of the FPGA, a constraint file needs to be added or created. In this design phase, there are two important hardware parameters we need to configure manually.
- Package Pin: Physical port position in Nexys4 DDR board.
    - [Power supplies](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual#power_supplies)
    - [Oscillators/Clocks](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual#oscillatorsclocks)
    - [Basic I/O](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual#basic_io) 
    - [Pmod Ports](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual#pmod_ports)
- I/O Std.: To fit real logical voltage in Nexys4 DDR board. Always choose `LVCMOS33` for Nexys4 DDR.

Configure all settings as below. ___Remember to save after every work___
![Imgur](https://i.imgur.com/DvKfo78.png)

Next, you can apply `Run Implementation`, `Generate Bitstream` seperately. Or, just click `Generate Bitstream` directly.
![Imgur](https://i.imgur.com/7qRD5e7.png)

Wait until you see the message "write_bitstream Complete" on the upper right corner.
![Imgur](https://i.imgur.com/TQkQItB.png)

Use USB cable to connect FPGA board to your computer and turn on the power.
![Imgur](https://i.imgur.com/y9gY67E.png)

Apply `Open Hardware Manager`.
![Imgur](https://i.imgur.com/Rakcfov.png)

Click `Open target` and choose `Auto connect`.
![Imgur](https://i.imgur.com/dyD1oIQ.png)
![Imgur](https://i.imgur.com/rWeKvga.png)

If nothing goes wrong, Vivado will fetch all information from FPGA borad.
![Imgur](https://i.imgur.com/Yhdnt5u.png)

Now, you can apply `Program device` to upload .bit file to the SRAM of the FPGA board. You can check the results by operating the FPGA board manually.
![Imgur](https://i.imgur.com/TBrnDq2.png)

[^first]:[https://en.wikipedia.org/wiki/Hardware_description_language](https://en.wikipedia.org/wiki/Hardware_description_language)
[^second]:[https://www.quora.com/How-can-I-get-started-with-learning-a-hardware-description-language](https://www.quora.com/How-can-I-get-started-with-learning-a-hardware-description-language)
[^third]:[https://www.quora.com/What-is-the-difference-between-hardware-description-language-hdl-and-assembly-language](https://www.quora.com/What-is-the-difference-between-hardware-description-language-hdl-and-assembly-language)
[^fourth]:[https://en.wikipedia.org/wiki/Verilog](https://en.wikipedia.org/wiki/Verilog)
[^fifth]:[http://athena.ecs.csus.edu/~arad/csc273/intro_verilog_hdl.pdf](http://athena.ecs.csus.edu/~arad/csc273/intro_verilog_hdl.pdf)
[^sixth]:[https://en.wikipedia.org/wiki/SystemVerilog](https://en.wikipedia.org/wiki/SystemVerilog)
[^seventh]:[http://athena.ecs.csus.edu/~arad/csc273/intro_verilog_hdl.pdf](http://athena.ecs.csus.edu/~arad/csc273/intro_verilog_hdl.pdf)
[^eighth]:https://en.wikipedia.org/wiki/Xilinx_Vivado
[^nineth]:Default system component collections![Imgur](https://i.imgur.com/iI1c14k.png)
[^tenth]: https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1
[^eleventh]:[Nexys A7: FPGA Trainer Board Recommended for ECE Curriculum](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual)
