---
# System prepended metadata

title: dv.1 (Create Design)
tags: [EDA tool, Verilog]

---

# dv.1 (Create Design)

###### Previous：[Design Vision (Intro)](/@C2N2/B1KM654Lgg)
###### Ｎext：[dv.2 (Design Environment 1)](/@C2N2/rkjnZj8Ulg)

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## 1. 分析 RTL 電路  (Analyze the Design)

1. **開啟分析視窗：==File== > ==Analyze==**
2. **匯入 RTL 電路：==Add== > ==選擇 RTL Code== > ==命名專案== > ==勾選選項== > ==OK==**
    <iframe src="https://drive.google.com/file/d/1b8rSVWvtvpqio49fWAi1ZxP-0ecKFBy7/preview" height="400"></iframe>

#### ● 分析電路時，==CMD== 會 ==顯示電路資訊==

- **載入的 ==標準元件 Library 路徑== & ==RTL Code 路徑== 資訊**
    :::spoiler ex：
    ```
    Loading db file '/home/.../slow.db'
    Loading db file '/home/.../fast.db'
    Loading db file '/home/.../tpz973gvwc.db'
    Loading db file '/home/.../tpz973gvtc.db'
    Loading db file '/home/.../tpz973gvbc.db'
    Loading db file '/usr/cad/.../dw_foundation.sldb'
    Loading db file '/usr/cad/.../gtech.db'
    Loading db file '/usr/cad/.../standard.sldb'
      Loading link library 'slow'
      Loading link library 'fast'
      Loading link library 'tpz973gvwc'
      Loading link library 'tpz973gvtc'
      Loading link library 'tpz973gvbc'
      Loading link library 'gtech'
    Loading verilog file '/home/.../file/CS.v'
    ```
    :::

- **==RTL 電路== 使用的 ==DFF== / ==Latch== 資訊**
    - **一個 ==RTL 電路== 有 ==多個 block==，會分別列出 ==block== 的 ==DFF== / ==Latch== 資訊**
    :::spoiler ex：
    ```
    ===============================================================================
    |    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
    ===============================================================================
    |       X8_reg        | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       X9_reg        | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
    |      X1_d_reg       | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       X1_reg        | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       X2_reg        | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       X3_reg        | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       X4_reg        | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       X5_reg        | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       X6_reg        | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       X7_reg        | Flip-flop |   8   |  Y  | N  | Y  | N  | N  | N  | N  |
    ===============================================================================
    ```
    :::
    :::spoiler ex：
    ```
    ===============================================================================
    |    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
    ===============================================================================
    |       S8_reg        | Flip-flop |  12   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       S9_reg        | Flip-flop |  12   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       S1_reg        | Flip-flop |  12   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       S2_reg        | Flip-flop |  12   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       S3_reg        | Flip-flop |  12   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       S4_reg        | Flip-flop |  12   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       S5_reg        | Flip-flop |  12   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       S6_reg        | Flip-flop |  12   |  Y  | N  | Y  | N  | N  | N  | N  |
    |       S7_reg        | Flip-flop |  12   |  Y  | N  | Y  | N  | N  | N  | N  |
    ===============================================================================
    ```
    :::
    :::spoiler ex：
    ```
    ===============================================================================
    |    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
    ===============================================================================
    |       Xt_reg        | Flip-flop |  12   |  Y  | N  | Y  | N  | N  | N  | N  |
    ===============================================================================
    ```
    :::

## 2. 建立 RTL 電路結構 (Elaborate the Design)

1. **開啟建構視窗：==File== > ==Elaborate==**
2. **==輸入專案名稱== > ==選擇專案== > ==OK==**
    <iframe src="https://drive.google.com/file/d/1su8GAQRCgZ-aUpQh3TU2d919TzBR4zzR/preview" height="400"></iframe>

#### ● 建構完成後，可以檢視 ==RTL 電路結構==

1. **開啟電路階層視窗：==Hierarchy== > ==New Logical Hierarchy View==**
    <iframe src="https://drive.google.com/file/d/1Hzu2MGwBiCazNT8djyhZSBFynYln924b/preview" height="400"></iframe>
2. **開啟電路視圖：==選擇電路== > ==Create Schematic of Selected Objects==**  
    - **==雙擊電路== 可以看到 ==內部電路==**
    <iframe src="https://drive.google.com/file/d/1yN3TS19JrEJAWy5GRi5jkl3DuCRabS8d/preview" height="300"></iframe>

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