---
# System prepended metadata

title: Design Vision (Intro)
tags: [EDA tool, Verilog]

---

# Design Vision (Intro)

###### Next：[dv.1 (Create Design)](/@C2N2/ByWb6adLee)

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> [!Note] **Design Vision**
> - **圖形化介面工具 (==GUI==)**
> - **用來輔助 ==RTL 分析==、==合成後檢查==、==電路結構檢視==、==時序分析== 等功能**
> - **是 [dc_shell <i class="ph ph-arrow-square-out"></i>](http://hackmd.io/@C2N2/rJOgEeNUgl) 的視覺化版本**


> [!Important] **呼叫 Design Vision**
> - **指令：**
>   > ```robotframework
>   > dv
>   > ```

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## 1. 建立 Design Vision 環境

### (1) 下載 ==Design Vision 環境==

```bash
cp /home/.../cshrc .cshrc 
source .cshrc
```

### (2) 設定 ==標準元件庫路徑==

```bash
mkdir Synthesis
cd Synthesis

cp /home/.../synopsys_dc.setup  .synopsys_dc.setup
```

### (3) 檢查 Library 路徑

- **開啟 ==Design Vision==**
  > ```robotframework
  > dv
  > ```

- **檢查路徑：==File > Setup==**
  <iframe src="https://drive.google.com/file/d/1AujjSHbXeExdyYQUjaBZGgNVhqjDlFl7/preview" height="300"></iframe>


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