---
# System prepended metadata

title: Regular Meeting (2021.1.18)
tags: [Regular Meeting, DeWei]

---

# Regular Meeting (2021.1.18)

1. Convert *XVC-IP(Official)* from *locked-ip* to *src-code-only-ip*
    * For higher flexibility customing our *xvc-ip* 
2. [Tips to reduce hardware build time](https://github.com/curly-wei/xvc-pynq-z2)

3. Little modification for sw of XVC-PYNQ 
    * *[CV-Qualifier](https://en.cppreference.com/w/cpp/language/cv)* 
        * *[volatile](http://newscienceview.blogspot.com/2013/09/c-volatile.html)*

    * [google style C++](https://google.github.io/styleguide/cppguide.html)

4. Progress: build sw

5. Problems about generate hw_targer for build sw

6. Architecture of XVC-PYNQ 

## 1 Convert *XVC-IP* from *locked-ip* to *src-code-only-ip*

### 1.1 Background

Since *XVC-IP(Official)* **has to checksum** before build it

We deprecate *locked-ip* of *XVC-IP(Official)*
We apply *src-code-only-ip* of *XVC-IP(Official)*

### 1.2 How to do

#### Step 1

In the `bd_system.tcl`(sub-shell for `top.tcl`),
From:
```tclsh
# Create instance: axi_jtag_0, and set properties
set axi_jtag_0 [ \
  create_bd_cell \
  -type ip -vlnv \
  A_Clark:Debug:axi_jtag:1.0 \
  axi_jtag_0 
]
```
Modify to :
```tclsh
# Create instance: axi_jtag_0, and set properties
set axi_jtag_0 [ \
  create_bd_cell \
  -type module -\
  reference axi_jtag_v1_0 \
  axi_jtag_0 ]
```

#### Step 2

Move out those files(`.v`) from ip source(archive file, zip)
![](https://i.imgur.com/vwynL6S.png)

to

``` bash
# pwd: root of xvc-pynq
./src/hw/hdl
```

and add this script into `top.tcl`

```tclsh
# in the top.tcl
#
#

set k_verilog_src_dir "../src/hw/hdl/"
#Read-in verilog files from source folder
set verilog_files [ glob -nocomplain "${k_verilog_src_dir}/*.v" ]
if { ${verilog_files} != "" } {
  read_verilog ${verilog_files}
  puts "INFO: read-in verilog files: ${verilog_files}"
}

```

### 1.3 Problem & Solution

#### Problem when building:

![](https://i.imgur.com/h92e4tA.png)

#### Solution:

Add 
```
# in top.tcl
set_property source_mgmt_mode All [current_project]
```
into the `top.tcl`

Regarding `source_mgmt_mode`, see
https://www.xilinx.com/support/answers/69846.html
If `source_mgmt_mode` hasn't set as 'All', then 
we can't compile `axi_jtage`*(xvc-ip)* with 'source code mode',
only can compile `axi_jtage` with 'locked ip mode'


## 4 Progress: build sw

Puropse:

Build petalinux(developed by Xilinx) and xvc-app(sw) to SD-Card

* Unfortunally, we need to build linux kernel for our board
    * ![](https://i.imgur.com/eIjT9jc.png)

Requirement:
* *.hwdef* file:
    * Generated from last of *top.tcl* (hw)
* Environment to build petalinux and xvc-app
    * OS: Linux only
    * shell: bash only

## 5 Problems about generate hw_targer for build sw
![](https://i.imgur.com/OIzQ3eC.png) 
* *write_hwdef* -> generate hw_targer for *SDK* -> OK
* *write_hw_platform* -> generate hw_targer for *Vitis* -> Failed
* *SDK* has been deprecated since *Vivado 2019.2*, now is *Vitis*
* [Seems no problem](https://forums.xilinx.com/t5/Embedded-Development-Tools/no-HDF-export-Vivado-2019-2/td-p/1042667)
* [I also post this problem to Xilinx forum](https://forums.xilinx.com/t5/Design-Entry/ERROR-Common-17-69-Command-failed-write-hw-platform-is-only/m-p/1195589)


## 6 Architecture of XVC-PYNQ

```graphviz
digraph G {
  rankdir = TB;
  labelloc = "t";
  label = "PYNQ-Z2 Board";
  color = black;
  
  DDR [ label = "DDR3\n512GByte", shape=Msquare ];
  
	subgraph cluster_zynq7000 {
	  newrank =true;
		label = "zynq7000 Soc"
    rankdir = LR;
    
		subgraph cluster_PS {
			node [ style = filled, color = white ];
			color = lightgrey;
			label = "Processor system \n (PS)";
			style = filled;
      rankdir = TB;
			
			arm_axi_if [ label = "AXI \n Interface" ];
			arm_proc [ label = "ARM \n  Processor" ];
			arm_mio [ label = "MIO" ];
			
			arm_axi_if -> arm_proc [ dir = both ];
			arm_proc -> arm_mio [ dir = both ];
		}

		subgraph cluster_PL {
			node [ style = filled ];
			color = blue;
			label = "Programming Logic \n (PL)";
      rankdir = TB;
      
			jtag_axi_if [ label = "JTAG-AXI \n Interface" ];
			jtag_axi_proc [ label = "JTAG \n Proc" ];
			
			jtag_axi_if -> jtag_axi_proc [ dir = both ];
		}
	  
		{ rank = same; jtag_axi_if; arm_axi_if; }
		jtag_axi_if -> arm_axi_if [ dir = both ];
		
	}
  
  DDR -> arm_proc [ dir = both ];
  
	eth_phy [ label = "Eth-PHY\nchip", shape=Msquare ];
	jtag_socket [ label = "JTAG-Socket\n(GPIO port)" ];
  RJ45_port [ label = "RJ45 port" ];
  
	jtag_axi_proc -> jtag_socket [ dir = both ];
	arm_mio -> eth_phy [ dir = both ];
  eth_phy -> RJ45_port [ dir = both ];
  
  
	{ rank = same; eth_phy;  jtag_socket; }
  { rank = same; DDR;  arm_proc; }
	
} 
```



* JTAG-PROC: Convert(Shifte) JTAG vector(32bits) (TDI_v, TDO_v, TMS_v, TCK_v) to JTAG signals (1bit)(TDI, TDO, TMS, TCK)

* JTAG-AXI-IF: Interface(IF) for access with processor

* PS: Access signal via etherner (port 2542) with *UNIX SOCKET* (sw & C code on Linux)

###### tags: `Regular Meeting` `DeWei`