# Regarding Equalizer of Transceiver on FPGA

## 1. Today's protagonist -- Equalizer (Serial)


* Working for *Serial Data Signal*

## 2. Introduction

### 2.1 Architecture in this article

digraph G {
  # Def var
  
  start [
    label="Problem with Decading of long trace"
  ]
  
  HF [
    label="emphasis HF"
  ]
  
  LF [
    label="supress LF"
  ]
  
  # link var
  start -> {HF,LF}
}

### 2.2. Solutions

#### 2.2.1. FIR(Finite Impulse Response) [2][3]


#### 2.2.2. Implement
* Tx:
* De-emphasis (FIR)
* Rx:
* CTLE(Continuous Time Linear Equalization)
* DFE(Feed Forward Equalization)

## 3. Problems with Longer Trace and Higher Trance-rate

### 3.1. Channel Insertion Loss

#### 3.1.1. Differential Insertion Loss of Sample Nelco 4000-13 Traces

#### 3.1.2. Ideal pulse respones (delta functuin in time-domain)

#### 3.1.3. Non-ideal pulse response

#### 3.1.4. Ideal/Non-ideal square wave response

Same case(loss) to chapter 3.1.3,

we use *square wave* as input:


It seems probe adjuster of oscillator:


#### 3.1.5. A example: sent/receive *01000*


### 3.2. Channel Discontinuity


* If $z2$ -> $\infty$, then $\frac{vt}{vi}$ -> $2$

* Picture shows response reflect in time-domain

### 3.3 My understanding

* I imagine this case as **Dispersion in Optics** (Although isn't accurate)

## 4. To solve this problem

### 4.1. In the Tx (De-emphasis)

#### 4.1.1. Without De-emphasis


#### 4.1.2. With De-emphasis (6dB ~= 2 times, *20dB???*)


#### 4.1.3. Circuit of De-emphasis (3-taps)


### 4.2. In the Rx

#### 4.2.1. CTLE(Continuous Time Linear Equalization)
* Basic concept of CTLE
* You could recognize as High-Pass Filter (with a little incorrect)
* Bad equalized of CTLE
* Correct-Equalized
* Under-Equalized
* Over-Equalized
* Transceiver of Xilinx's FPGA provide "Dynamic Auto Adaptation" for CTLE (additional power consump ~= 5%)
* cons: noise could be amplify

#### 4.2.2. DFE(Feed Forward Equalization)

* Circuit of DFE (16 taps in ultrascle-series)
* DFE works
* DFE has good performance to reject noise
* Data for DFE input *must be random (Low probability of repetition)*, CTLE is not. So UG578[4] recommand DFE coporate with 8B/10B(64B/66B) encoding
* Lots of case (10GbE, PCI-E) default to use DFE

## 5. Summery

* Problems: Signal decade of Long-Trace
* Due to
* Channel Insertion Loss (Dispersion)
* Channel Discontinuity (Reflection)
* Solutions
* Emphasis HF and Supress LF
* Tx
* De-emphasis (FIR)
* Rx
* CTLE (High-Pass Filter)
* DFE (Similer to FIR)
* Manually select parameter of CTLE and DFE is critical
* Xilinx's transceiver also support DFE+CTLE

## 6. Note: Regarding "Insertion loss at Nyquist" of ibertGTY IP

PG196[5] said:


## Reference

[1]
[Equalization for High-Speed Serial Interfaces in Xilinx 7 Series FPGA Transceivers](https://www.xilinx.com/support/documentation/white_papers/wp419-7Series-XCVR-Equalization.pdf)

[2]
[Finite impulse response (wiki)](https://en.wikipedia.org/wiki/Finite_impulse_response)

[3]
[Finite impulse response (video)](https://youtu.be/NvRKtdrssFA)

[4]
[p210, UG578, UltraScale Architecture GTY Transceivers](https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf)

[5]
[p14, PG196, IBERT for UltraScale GTY Transceivers v1.2](https://www.xilinx.com/support/documentation/ip_documentation/ibert_ultrascale_gty/v1_2/pg196-ibert-ultrascale-gty.pdf)

###### tags: `TechReport` `DeWei`