---
# System prepended metadata

title: Regular Meeting (2020.12.7)
tags: [Regular Meeting, DeWei]

---

# Regular Meeting (2020.12.7)

* Testing opt. modules with all GTY bank (8 modules) on UT4
    * https://hackmd.io/@BelleII-CDC-Trig-NTU-DeWei/B12VMTjSv
    * A few errors
    * to swap opt. moduled

*  Xilinx Virtual Cable (XVC) vs UT4 confg.
    * Reduced version! 
    * If anything missed, tell me I'll append


## Xilinx Virtual Cable (XVC) vs UT4 confg.

![](https://i.imgur.com/9kEWp5R.png)

* Advantage
    * Cost of chip: $-Artrix-7 ~= $-Zynq-7 (about 2K NTD)
    * Versatile:
        * Artrix-7 solutions: 
            * Pure FPGA
        * Zynq-7 solutions: 
            * SoC (FPGA + ARM-CPU)
            * Simple controll/access to main FPGA via eth. (Ready made IP)
    * Zynq-7 solutions don't need VME, just need eth. cables & sw.
        * cost down for system
    * Both Programming VHDL-code has significant difference
        * Artrix-7 solutions:
            * Pure HDL code (JTAG <-> Ethernet)
            * Ready-made IP ????
        * Zynq-7 solutions: 
            * HDL code(FPGA) + C code(CPU) 
            * has ready-made IP and C code for programming!!

* In the beginning of development, I recommand use develop board
![image alt](https://i.imgur.com/GiV7PvD.png)

* Note: *XVC* is similar to *SmartLynq*, but completed diffrent things
    * Both needs Zynq-SoC, programming with eth.
    * But difference
        * Protocal
            * *XVC* use port 3121, 
            * *SmartLynq* use port 2542
        * Hawdware Server(HW server)
            * for *XVC*, HW server in the PC
            * for *SmartLynq*, HW server in the Zynq-Soc

* Reference
    * https://hackmd.io/@BelleII-CDC-Trig-NTU-DeWei/H1Tsveg9D

###### tags: `Regular Meeting` `DeWei`