---
# System prepended metadata

title: Regular Meeting (2020.5.11)
tags: [Regular Meeting, DeWei]

---

# Regular Meeting (2020.5.11)

## Outline

* Reason why Optical Modules does not worked

![](https://i.imgur.com/WgKvnub.png)
![](https://i.imgur.com/R4ozhgC.png)

* Staring writte code for *USER-DATA-Transceiver*
    * Basic architecture using my MS-Degree themes with 64B/66B En/Decoder
    * Duration: estimate 2~3 weeks
    * I'd like to coding with `verilog / system-verilog compiler`


###### tags: `Regular Meeting` `DeWei`