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# System prepended metadata

title: Regarding UT4

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# Regarding UT4

## Main difference between UT3 and UT4

* FPGA-chip: Virtex-6 -> Virtex-UltraScale
* Transcivers and opt. modules: 
    * keeps 48 channels
    * 10Gbps -> 16Gbps(24 channels) & 25Gbps(24 channels)
    * Higher capacity of LUT/RAM
* IDE: ISE -> vivado(tcl-script)
* Power consumption: 25W~50W -> ~100W (VME-spec is 100w per board)

## Structure of UT4

![image alt](https://i.imgur.com/pmBOSm6.png)

## Test ibert for UT4

![image alt](https://i.imgur.com/MI8UvEh.png)

GTY:
![](https://i.imgur.com/Xiy4236.png)

## Target

1. Implement UT3 code to UT4
    * I'm implementing a part (2D-tracker) of UT3 now
2. Optimize UT4