# Regarding UT4

## Main difference between UT3 and UT4

* FPGA-chip: Virtex-6 -> Virtex-UltraScale
* Transcivers and opt. modules:
* keeps 48 channels
* 10Gbps -> 16Gbps(24 channels) & 25Gbps(24 channels)
* Higher capacity of LUT/RAM
* IDE: ISE -> vivado(tcl-script)
* Power consumption: 25W~50W -> ~100W (VME-spec is 100w per board)

## Structure of UT4


## Test ibert for UT4


GTY:

## Target

1. Implement UT3 code to UT4
* I'm implementing a part (2D-tracker) of UT3 now
2. Optimize UT4