---
# System prepended metadata

title: Comparison between ZedBoard and Nexys
tags: [purchase]

---

# Comparison between ZedBoard and Nexys
* FPGA
  * ZedBaord -> Zynq-7000 *aka FPGA+SOC*
  * Nexys -> Artix-7 *aka pure FPGA*
* *Nexys*
  * Now CDCFE-Group (Prototype-FW) used
  * Resource seems to be **scarce (RAM)**
  * Now FW summery which is generated by Vivado:
    * ![](https://i.imgur.com/O9aE7om.png)
    * ![](https://i.imgur.com/8sgzZpc.png)
    * I guess because of *FIFO*
      * FIFO is generally used for read-in/buffer of data
* If Replace *Nexys* with *ZedBoard*
  * Larger than Nexys
    * RAM: 365Kb -> 4.9Kb
  * Smaller than Nexys
    * LUT block: 215K -> 85K
      * looking up summery, it seems to be enough
    * DSP slice: 740 -> 220
      * We can't use in our present project
    * Quantity of I/O: PL(285) -> PL(200) + PS(128) 
      * It also seems to be enough for our case
* FMC
  * Have compared pin-assignment -> Matched ,no problem
    * ZedBaord <-> CDCFE-PT
    * Nexys <->CDCFE-PT
  * Difference: [Transceiver(GTX) pin](https://support.xilinx.com/s/question/0D52E00006hpX8oSAE/fmc-zcu102?language=en_US)
    * ![](https://i.imgur.com/6scfoEZ.png)
    * ![](https://i.imgur.com/Qy6CIvj.png)
* ETH
  * Nexys -> [SiTCP](https://www.bbtech.co.jp/en/sitcp/)
  * ZedBoard -> SiTCP(PL) or PS-TCP(Linux/OS)
    * ~10 port for Eth if using SiTCP
###### tags: `purchase`