---
# System prepended metadata

title: Regular Meeting (2022.8.22)
tags: [Regular Meeting, DeWei]

---

# Regular Meeting (2022.8.22)
* CDCFE Fanout Baord
  * Status pending
    * fix unsuitable hole on lastweek
  * Decision whether to AC couple
  * 50-ohm on PCB-Board
* Zybo-z7

## CDCFE Fanout Baord

### Fix unsuitable hole on lastweek 

Before:
![](https://i.imgur.com/jDaKafI.png)

After:
![](https://i.imgur.com/YT9iIP7.png)

* Above footprint is provided by kicad

### Decision whether to AC couple

* Keeping DC info?
  * Yes/No
* Is DC bias (XXmV) noise? Can it impact dynamic range?
  * No
* Does we need to shift (DC) level?
  * No

### 50-ohm on PCB-Board 

* Calculator provide by kicad
  * ![](https://i.imgur.com/7MYwd5v.png)
  * H << -> W << to fit 50-ohm trace
  * So, more layers is good to implement thin signal trace because of H <<

* Manufactor:
  * ![](https://i.imgur.com/eaRrViy.png)
* old: 
  * ![](https://i.imgur.com/Ww0pD0Q.png)
  * ![](https://i.imgur.com/C7qnAx4.png)
* New: Trace length of signal from 0.25mm to 0.55mm
  * ![](https://i.imgur.com/BjJt3NR.png)


## Zybo-z7

* Mergering Ramdisk

###### tags: `Regular Meeting` `DeWei`