# Regular Meeting (2022.8.22)
* CDCFE Fanout Baord
* Status pending
* fix unsuitable hole on lastweek
* Decision whether to AC couple
* 50-ohm on PCB-Board
* Zybo-z7

## CDCFE Fanout Baord

### Fix unsuitable hole on lastweek

Before:

After:

* Above footprint is provided by kicad

### Decision whether to AC couple

* Keeping DC info?
* Yes/No
* Is DC bias (XXmV) noise? Can it impact dynamic range?
* No
* Does we need to shift (DC) level?
* No

### 50-ohm on PCB-Board

* Calculator provide by kicad
* 
* H << -> W << to fit 50-ohm trace
* So, more layers is good to implement thin signal trace because of H <<

* Manufactor:
* 
* old:
* 
* 
* New: Trace length of signal from 0.25mm to 0.55mm
* 

## Zybo-z7

* Mergering Ramdisk

###### tags: `Regular Meeting` `DeWei`