# Customing our low cost *SmartLynq* (Evaluation)

## 1 Background


Xilinx *SmartLynq* is good to use,

[reason see here](https://hackmd.io/@BelleII-CDC-Trig-NTU-DeWei/S1ZpCJJqv)

But.....it's too expensive... (*~18000 NTD*)

**Could I make it with *Low-Cost*?**

## 2 Hardware of *SmartLynq*

### 2.1 Disassemble *SmartLynq* (by someone japanese)

Here looking like inverse engineering

Refer to

[here](http://nahitafu.cocolog-nifty.com/nahitafu/2020/08/post-f54b6f.html)

and

[here](http://nahitafu.cocolog-nifty.com/nahitafu/2020/08/post-886b20.html)

The marjor component of *SmartLynq* is *Zynq7000* FPGA,

*(XC7Z010のCLG400)*

which price is (from digikey)


* Others more important compoment
* 256Mb DDR3-1866 RAM (~300NT) \*2 + 256M DDR2-800 RAM (<1NT)*1
* 128Mb QSPI eMMC

### 2.2 Summary of *SmartLynq* hardware

I think (hardware) cost of *SmartLynq* should *<5000 NTD*

Even *<3000 NTD*,

if we configure it to board such as UT4

(To replace Artrix-7 with Zynq-7)

## 3 *Xilinx Virtual Cable* (*XVC*)

It's similar to *SmartLynq*,

but it's not same to *SmartLynq*.

Use *Xilinx Virtual Cable* (*XVC*)

which needs to closed cooperate with its hardware,

firmware and software.

To Connect to programming board from remote PC,

with the *SmartLynq*:

vivado% open_hw_manager
vivado% connect_hw_server -url TCP:<init-ip-addr>:3121
vivado% open_hw_target #implicate host <init-ip-addr>:3121

with the *XVC*:

vivado% open_hw_manager
vivado% connect_hw_server # implicate localhost
vivado% open_hw_target -xvc_url 192.168.10.1:2542

Refer to [here](https://www.xilinx.com/support/documentation/application_notes/xapp1251-xvc-zynq-petalinux.pdf)

### 3.1 Summary of *Xilinx Virtual Cable*

* BOM of Hardware (first evaluation)
* Xilinx Zynq soc (FPGA + ARM-CPU)
* RAM ~512MB (for CPU)
* microSD ~ 1GB (boot zynq-soc)

* There port different to *Xilinx-SmartLynq-Cable*
(2542 vs 3121)
So I think basic function (*XVC*)
also different to *Xilinx-SmartLynq-Cable*

### 3.2 Compare *SmartLynq* with *XVC*


## 4 Hardware suggesion:

### 4.1 Example doc. of *Xilinx Virtual Cable* used


* [official site](http://zedboard.org/product/microzed)

* Hard to buy
* I'm not sure whether e-element provided

* FPGA (same to *SmartLynq*)

[Datasheet refer to here](http://zedboard.org/sites/default/files/documentations/MicroZed_GettingStarted_v1_2.pdf)

### 4.2 Or *Pynq-z2*

[official site](http://www.e-elements.com/tw/product/show/id/133.shtml)

* e-element official provided

* FPGA (better than *SmartLynq*) 

* More I/O pins

[Datasheet refer to here](https://d2m32eurp10079.cloudfront.net/Download/PYNQ_Z2_User_Manual_v1.1.pdf)

## 5 Compare soution to FPGA of Belle-II CDC-Trig


## 6 Note

UT4 can't implement with this solution,

because 2nd FPGA of UT4 is **Artrix-7**, not Zynq7000

(This function needs ARM-CPU with Xilinx-Zynq-IP)

## 7 Summery

* *SmartLynq* is similar to *XVC*:
* Both requires Xilinx-Zynq-Soc and its peripherals(RAM/Flash))
* Both of them not only can be programming to main FPGA,
but also can do simple control/IO/Access

But they're actually completely difference

* UT4 can't programming with *XVC*
since its 2nd FPGA is Artrix-7-FPGA
not Zynq-Soc

* We can buy pynq-z2 to play and evaluation XCV function first.
* cost ~5k NTD

If no problem, configure it to new board.
* cost should <3k NTD

###### tags: `Evaluation Report` `DeWei`