# Regular Meeting (2020.7.26)

* Reduce build.tcl with Makefile
* Checking if the file exists is now granted to `make` from `tcl`
* Problem: make (top-dir) -> make (sub-dir) -> gcc/vivado
*( Not a good solution)
* ~~call top-dir make, can't check sub-dir deps.~~
* ~~Solution: `find` search all deps. in top-dir make~~
* ~~Solution: using `.mk` file return deps.~~
## Reduce build.tcl with Makefile

Original build_hw`.tcl`:

#Read-in verilog files from source folder
foreach verilog_file ${kVerilogFiles} {
  if { [file exists ${verilog_file} ] } {
    read_verilog ${verilog_file}
    puts [InfoStr "read-in src-verilog files: \n ${verilog_file}"]
  } else {
    error [ErrStr "${verilog_file} does not exist" ]
  }
}

# other phase: xdc/verilog

Now build_hw`.tcl`

read_verilog ${verilog_files}

~~Because~~

verilog_files := a.v b.v c.v 
Deps := ${verilog_files} ${xdc_files} ${etc_files} 

build_hw: ${Hw_target}
${Hw_target}: ${Deps}

~~if one of `Deps` loss, then `make` will raise error which seems to~~

make[1]: *** No rule to make target 
'/home/dewei/Documents/xvc-zybo-z7/src/hw/hdl/a.v', 
needed by 'compile'.  Stop.
make[1]: Leaving directory '/home/dewei/Documents/xvc-zybo-z7/src/hw'
make: *** [Makefile:142: a.v] Error 2

### Reduced lines
* 350-lines -> 200-lines for `build_hw.tcl`
* add 100 lines for makefile

###### tags: `Regular Meeting` `DeWei`