---
# System prepended metadata

title: Seg Display

---

# Seg Display 
●　作業標題：(Excess-3/Decimal) to 7-seg Display with Preset/Reset
●　班級姓名座號：國立高雄大學電機系大四 A1105107 莊庭勛
●　授課老師：林宏益教授
# 一、作業內容：
(Excess-3/Decimal) to 7-seg Display with Preset/Reset

# 二、實作步驟：

##  1.撰寫 Verilog code

    
        module Seven_SEg(Reset_n,A,B,C,D,excess,preset,Seg);
        input preset;
        input Reset_n;
        input excess;
	    input A,B,C,D;
	    output [7:0] Seg;
	    reg [3:0] In;
	    reg [7:0] Seg;
    
	    always @(*)  begin
    
        In = {D,C,B,A};
		if (Reset_n == 0)
			Seg=8'b11010101; //0x91,n
		else begin
		   if  (excess && ~preset)begin
		      case(In)
			  4'b0000: Seg=8'b00001101; //0x0d,3
			  4'b0001: Seg=8'b10011001; //0x99,4
			  4'b0010: Seg=8'b01001001; //0x49,5
			  4'b0011: Seg=8'b01000001; //0x41,6
			  4'b0100: Seg=8'b00011111; //0x1f,7
			  4'b0101: Seg=8'b00000001; //0x01,8
			  4'b0110: Seg=8'b00001001; //0x09,9
			  4'b0111: Seg=8'b00010001; //0x11,A
			  4'b1000: Seg=8'b11000001; //0xc1,b
			  4'b1001: Seg=8'b11100101; //0xe5,c
			  4'b1010: Seg=8'b10000101; //0x85,d
			  4'b1011: Seg=8'b01100001; //0x61,E
			  4'b1100: Seg=8'b01110001; //0x71,F
			  
			  4'b1101: Seg=8'b11111101; //0x61,-
			  4'b1110: Seg=8'b11111101; //0x71,-
			  4'b1111: Seg=8'b11111101; //0x61,-
			endcase
		end
			else if (~excess && ~preset)begin
			case(In)
			  4'b0000: Seg=8'b00000011; //0x03,0
			  4'b0001: Seg=8'b10011111; //0x9f,1
			  4'b0010: Seg=8'b00100101; //0x25,2
			  4'b0011: Seg=8'b00001101; //0x0d,3
			  4'b0100: Seg=8'b10011001; //0x99,4
			  4'b0101: Seg=8'b01001001; //0x49,5
			  4'b0110: Seg=8'b01000001; //0x41,6
			  4'b0111: Seg=8'b00011111; //0x1f,7
			  4'b1000: Seg=8'b00000001; //0x01,8
			  4'b1001: Seg=8'b00001001; //0x09,9
			  4'b1010: Seg=8'b00010001; //0x11,A
			  4'b1011: Seg=8'b11000001; //0xc1,b
			  4'b1100: Seg=8'b11100101; //0xe5,c
			  4'b1101: Seg=8'b10000101; //0x85,d
			  4'b1110: Seg=8'b01100001; //0x61,E
			  4'b1111: Seg=8'b01110001; //0x71,F
			endcase
			end
			else 
			     Seg=8'b00110001;   //0x71,P
		end
        end
        endmodule
## 2. 撰寫 testbench
                           
                               module test_tb;
	        
            reg   Reset_n,preset,excess,A,B,C,D;
	
            wire [7:0] Seg;

            initial
	        begin
		    Reset_n = 1'b1; preset = 1'b0; excess = 1'b0;
		    D = 1'b0; C = 1'b0; B =1'b0; A = 1'b0;
		    #50 D = 1'b0; C = 1'b0; B =1'b0; A = 1'b1;
		    #50 D = 1'b0; C = 1'b0; B =1'b1; A = 1'b0;
		    #50 D = 1'b0; C = 1'b0; B =1'b1; A = 1'b1;
		    #50 D = 1'b0; C = 1'b1; B =1'b0; A = 1'b0;
		    #50 D = 1'b0; C = 1'b1; B =1'b0; A = 1'b1;
		    #50 D = 1'b0; C = 1'b1; B =1'b1; A = 1'b0;
		    #50 D = 1'b0; C = 1'b1; B =1'b1; A = 1'b1;
		    #50 D = 1'b1; C = 1'b0; B =1'b0; A = 1'b0;
		    #50 D = 1'b1; C = 1'b0; B =1'b0; A = 1'b1;
		    #50 D = 1'b1; C = 1'b0; B =1'b1; A = 1'b0;
		    #50 D = 1'b1; C = 1'b0; B =1'b1; A = 1'b1;
		    #50 D = 1'b1; C = 1'b1; B =1'b0; A = 1'b0;
		    #50 D = 1'b1; C = 1'b1; B =1'b0; A = 1'b1;
		    #50 D = 1'b1; C = 1'b1; B =1'b1; A = 1'b0;
		    #50 D = 1'b1; C = 1'b1; B =1'b1; A = 1'b1;
                //.............................................................................Excess.........................................................//
		    #50 Reset_n = 1'b1; preset = 1'b0; excess = 1'b1;
		    D = 1'b0; C = 1'b0; B =1'b0; A = 1'b0;
		    #50 D = 1'b0; C = 1'b0; B =1'b0; A = 1'b1;
		    #50 D = 1'b0; C = 1'b0; B =1'b1; A = 1'b0;
		    #50 D = 1'b0; C = 1'b0; B =1'b1; A = 1'b1;
		    #50 D = 1'b0; C = 1'b1; B =1'b0; A = 1'b0;
		    #50 D = 1'b0; C = 1'b1; B =1'b0; A = 1'b1;
		    #50 D = 1'b0; C = 1'b1; B =1'b1; A = 1'b0;
		    #50 D = 1'b0; C = 1'b1; B =1'b1; A = 1'b1;
		    #50 D = 1'b1; C = 1'b0; B =1'b0; A = 1'b0;
		    #50 D = 1'b1; C = 1'b0; B =1'b0; A = 1'b1;
		    #50 D = 1'b1; C = 1'b0; B =1'b1; A = 1'b0;
		    #50 D = 1'b1; C = 1'b0; B =1'b1; A = 1'b1;
		    #50 D = 1'b1; C = 1'b1; B =1'b0; A = 1'b0;
		    #50 D = 1'b1; C = 1'b1; B =1'b0; A = 1'b1;
		    #50 D = 1'b1; C = 1'b1; B =1'b1; A = 1'b0;
		    #50 D = 1'b1; C = 1'b1; B =1'b1; A = 1'b1;
            //.............................................................................n  .........................................................//
            #50 Reset_n = 1'b0; preset = 1'b0; excess = 1'b1;
		    D = 1'b0; C = 1'b0; B =1'b0; A = 1'b0;
		    #50 D = 1'b0; C = 1'b0; B =1'b0; A = 1'b1;
		    #50 D = 1'b0; C = 1'b0; B =1'b1; A = 1'b0;
		    #50 D = 1'b0; C = 1'b0; B =1'b1; A = 1'b1;
		    #50 D = 1'b0; C = 1'b1; B =1'b0; A = 1'b0;
		    #50 D = 1'b0; C = 1'b1; B =1'b0; A = 1'b1;
		    #50 D = 1'b0; C = 1'b1; B =1'b1; A = 1'b0;
		    #50 D = 1'b0; C = 1'b1; B =1'b1; A = 1'b1;
		    #50 D = 1'b1; C = 1'b0; B =1'b0; A = 1'b0;
		    #50 D = 1'b1; C = 1'b0; B =1'b0; A = 1'b1;
		    #50 D = 1'b1; C = 1'b0; B =1'b1; A = 1'b0;
		    #50 D = 1'b1; C = 1'b0; B =1'b1; A = 1'b1;
		    #50 D = 1'b1; C = 1'b1; B =1'b0; A = 1'b0;
		    #50 D = 1'b1; C = 1'b1; B =1'b0; A = 1'b1;
		    #50 D = 1'b1; C = 1'b1; B =1'b1; A = 1'b0;
		    #50 D = 1'b1; C = 1'b1; B =1'b1; A = 1'b1;
	        //.............................................................................p  .........................................................//	
	       #50 Reset_n = 1'b1; preset = 1'b1; excess = 1'b1;
		    D = 1'b0; C = 1'b0; B =1'b0; A = 1'b0;
		    #50 D = 1'b0; C = 1'b0; B =1'b0; A = 1'b1;
		    #50 D = 1'b0; C = 1'b0; B =1'b1; A = 1'b0;
		    #50 D = 1'b0; C = 1'b0; B =1'b1; A = 1'b1;
		    #50 D = 1'b0; C = 1'b1; B =1'b0; A = 1'b0;
		    #50 D = 1'b0; C = 1'b1; B =1'b0; A = 1'b1;
		    #50 D = 1'b0; C = 1'b1; B =1'b1; A = 1'b0;
		    #50 D = 1'b0; C = 1'b1; B =1'b1; A = 1'b1;
		    #50 D = 1'b1; C = 1'b0; B =1'b0; A = 1'b0;
		    #50 D = 1'b1; C = 1'b0; B =1'b0; A = 1'b1;
		    #50 D = 1'b1; C = 1'b0; B =1'b1; A = 1'b0;
		    #50 D = 1'b1; C = 1'b0; B =1'b1; A = 1'b1;
		    #50 D = 1'b1; C = 1'b1; B =1'b0; A = 1'b0;
		    #50 D = 1'b1; C = 1'b1; B =1'b0; A = 1'b1;
		    #50 D = 1'b1; C = 1'b1; B =1'b1; A = 1'b0;
		    #50 D = 1'b1; C = 1'b1; B =1'b1; A = 1'b1;
		    #50 $finish;
	        end
	        Seven_SEg S(Reset_n,A,B,C,D,preset,excess,Seg);
            endmodule



下圖為 Reset_n為1 Preset為1 的情況 
![image](https://hackmd.io/_uploads/Sy3228Cx1e.png)

下圖為Reset_n為0 Preset為x 的情況 以及 Reset_n為1 Preset為1的情況
![image](https://hackmd.io/_uploads/S1S9TIRxke.png)

# 三. 開啟 Xilinx Vivado 並進行 Synthesis, Implementation ,Generate bitstream
![image](https://hackmd.io/_uploads/Byxh7Gt-kx.png)
![image](https://hackmd.io/_uploads/Bk-Z4MF-kl.png)


# 四.更改所使用板子的 .xdc檔案中的 I/O 腳位最後進行燒錄
![image](https://hackmd.io/_uploads/B1NrQGFWJe.png)
![image](https://hackmd.io/_uploads/HJGImftZ1e.png)
![image](https://hackmd.io/_uploads/ByiImMKZ1l.png)
![image](https://hackmd.io/_uploads/SkuwXfYZyg.png)

# 五.實作結果

Reset_n = 0 Preset = 0 時顯示為n
![image](https://hackmd.io/_uploads/HJa6VwCgyx.png)
Reset_n = 0 Preset = 1 時顯示為n
![image](https://hackmd.io/_uploads/ryQWBv0x1e.png)
Reset_n = 1 Preset = 1 時顯示為p
![image](https://hackmd.io/_uploads/r1_XrPCeye.png)
Reset_n = 1 Preset = 0  excess = 0 時顯示為 0
![image](https://hackmd.io/_uploads/SJ0BSv0l1x.png)

Reset_n = 1  Preset = 0 excess = 0的影片(檔案太大 hackMD無法上傳) 用youtube short
https://www.youtube.com/shorts/PMNmCRBfYhM

Reset_n = 1  Preset = 0 excess = 1的影片(檔案太大 hackMD無法上傳) 用youtube short
https://youtube.com/shorts/LEIt15DGOGs

Schematic

![image](https://hackmd.io/_uploads/rkm0HDCxkl.png)



四、實驗心得：


本次的作業在撰寫 Verilog 的部分不算過於困難，testbench時也是很快地跑出正確的模擬
但是在FPGA實作時，所用的七段顯示器為共陽極，所以在高準位時不會亮 
所以要立即更改code，再來在進行Excess腳位設定的時候是用PMODB的腳位進行input
但其實此腳位在設定0或1時，要將其接上板子上的VDD和GND，才能夠正常顯示，我原本是將其接在麵包版上的VDD和GND導致無法正常運作

五、參考文獻：

EEF946〈軟硬體協同設計〉課堂參考講義

      
