---
# System prepended metadata

title: LLVM Backend
tags: [backend, code generation, llvm]

---

# LLVM Backend
###### tags: `llvm` `backend` `code generation`
## How to add target 
1. add your target into `lib/Target`
    * e.g: lib/Target/`TEMP`
2. add the target [td](https://llvm.org/docs/TableGen/index.html)    
    - TableGen would eat td file to generate XXX`GenRegisterInfo.inc` file included by C++
    * `TEMP.td`
    * `TEMPRegisterInfo.td` -[defining-a-register](https://llvm.org/docs/WritingAnLLVMBackend.html#defining-a-register)
        ```td=
        // for assembly code with opcode
		class TEMPReg<bits<16> Enc, string n> : Register<n> {
		  let HWEncoding = Enc;
		  let Namespace = "TEMP";
		}
		
		//  regular registers 
        /*  */
		def R0 : TEMPReg< 0, "r0">, DwarfRegNum<[0]>;
		def R1 : TEMPReg< 1, "r1">, DwarfRegNum<[1]>;
		def R2 : TEMPReg< 2, "r2">, DwarfRegNum<[2]>;
		def R3 : TEMPReg< 3, "r3">, DwarfRegNum<[3]>;
		def R4 : TEMPReg< 4, "r4">, DwarfRegNum<[4]>;
        ...
        
        // System registers
        def PC : TEMPReg< 12, "pc">, DwarfRegNum<[12]>;
        def SP : TEMPReg< 13, "sp">, DwarfRegNum<[13]>;
        def RETREG : TEMPReg< 14, "retreg">, DwarfRegNum<[14]>;
            
        // branch registers
        def PR0 : TEMPReg<1, "pr0">, DwarfRegNum<[22]>;
		def PR1 : TEMPReg<2, "pr1">, DwarfRegNum<[23]>;
		def PR2 : TEMPReg<3, "pr2">, DwarfRegNum<[34]>;
        ...
        
        // class register
        // class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
        //            dag regList, RegAltNameIndex idx = NoRegAltName>
                    
        // general purpose register file or GPR
        def GPR : RegisterClass<"TEMP", [XLenVT], 32, (add
		    (sequence "R%u", #, #),
		    (sequence "R%u", #, #),
		    (sequence "R%u", #, #),
		    (sequence "R%u", #, #),
		    (sequence "R%u", #, #),
		    (sequence "R%u", #, #)
		  )> {
		  let RegInfos = RegInfoByHwMode<
		      [RV32,              RV64,              DefaultMode],
		      [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
		}
        def GRF : RegisterClass<"TEMP", [i32], 32, (sequence "R%u", 0, 23)>;
        
        /** options - https://en.wikipedia.org/wiki/Register_file
         *  rename register file (RRF)
         *  architected register file (ARF)
         *  special register file (SRF)
         *  accumulator register (ACR)
         *  physical register file (PRF)
         *  system refgister file (SRF)
         *  predicate register file (PRF)
         */
        ```
        * tablegen will generate `TEMPRegister.inc`
        ```inc
        
        ```
    * `TEMP`RegisterInfo.cpp
    * `TEMP`RegisterInfo.h
    * LLVMBuild.txt
        ```txt=
        [common]
		subdirectories = 
		
		[component_0]
		type = TargetGroup
		name = TEMP
		parent = Target
		has_asmprinter = 1
		has_disassembler = 1
		
		[component_1]
		type = Library
		name = TEMPCodeGen
		parent = TEMP
		required_libraries = Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel TransformUtils
		add_to_library_groups = TEMP
        ```
    * CMakeLists.txt
    * MCTargetDesc/`TEMT`MCTargetDesc.h