---
# System prepended metadata

title: TP Modul 9 - Microprogramming

---

# TP Modul 9 - Microprogramming 

> Pembuat Soal: AX

```txt
Nama : M. Avicenna Raffaiz Adiharsa
NPM  : 2206062844
```

## Teori (30 pts)

### 1. Jelaskan perbedaan control unit dengan menggunakan microprogramming dan FSM (hardwired) (15 poin)


![image](https://hackmd.io/_uploads/BJnBXDKg-l.png)

Microprogramming: Unit kontrol menggunakan memori (program internal CPU) untuk menyimpan langkah-langkah mikro. Keunggulan: fleksibel dan mudah dimodifikasi. Kekurangan: lebih lambat

Hardwired (FSM): Unit kontrol berupa rangkaian logika digital murni (gerbang, decoder, flip-flop) yang langsung menghasilkan sinyal kontrol. Keunggulan: kecepatan tinggi. Kekurangan: sulit dimodifikasi jika set instruksi berubah.

### Referensi

- Difference Between Hardwired and Microprogrammed Control Unit
 [Online]. Available: <https://www.geeksforgeeks.org/computer-organization-architecture/difference-between-hardwired-and-microprogrammed-control-unit>. [Diakses: 18-Sep-2025]
- Difference between Hardwired and Micro-programmed Control Unit | Set 2
 [Online]. Available: <https://www.geeksforgeeks.org/computer-organization-architecture/difference-between-hardwired-and-micro-programmed-control-unit-set-2>. [Diakses: 18-Sep-2025]
 
### 2. Apa keuntungan menggunakan microprogramming dibanding dengan FSM (hardwired) (15 poin)

[jawaban]


### Referensi

- Difference Between Hardwired and Microprogrammed Control Unit
 [Online]. Available: <https://www.geeksforgeeks.org/computer-organization-architecture/difference-between-hardwired-and-microprogrammed-control-unit>. [Diakses: 18-Sep-2025]
- Difference between Hardwired and Micro-programmed Control Unit | Set 2
 [Online]. Available: <https://www.geeksforgeeks.org/computer-organization-architecture/difference-between-hardwired-and-micro-programmed-control-unit-set-2>. [Diakses: 18-Sep-2025]
- Microprogramming vs. Hardwired Control [Online]. Available: <https://study.com/academy/lesson/microprogramming-vs-hardwired-control.html>. [Diakses: 18-Sep-2025]
 

## Praktik (70 pts)
Buka kembali code LP8 yang kalian kerjakan dan pastikan bahwa semua tabel control wordnya sudah benar (TP + CS) yang berarti total ada 12 instruction : 
- LDA 

| CC | RAO | RAI | RBO | RBI | SUB | ALO | PCI | PCO | CNT | MRI | RMI | RMO | IRI | IRO |
|----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
| 1  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  1  |  0  |  0  |  0  |  1  |
| 2  |  0  |  1  |  0  |  0  |  0  |  0  |  0  |  0  |  1  |  0  |  0  |  1  |  0  |  0  |

- STA

| CC | RAO | RAI | RBO | RBI | SUB | ALO | PCI | PCO | CNT | MRI | RMI | RMO | IRI | IRO |
| :--------: | :---------: | :---------: | :---------: | :---------: | :---------: | :---------: | :---------: | :---------: | :---------: | :---------: | :---------: | :---------: | :---------: | :---------: |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |

- LDB

| CC | RAO | RAI | RBO | RBI | SUB | ALO | PCI | PCO | CNT | MRI | RMI | RMO | IRI | IRO |
|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |

- STB

| CC | RAO | RAI | RBO | RBI | SUB | ALO | PCI | PCO | CNT | MRI | RMI | RMO | IRI | IRO |
|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | **1** | 0 | 0 | 0 | **1** |
| 2 | 0 | 0 | **1** | 0 | 0 | 0 | 0 | 0 | **1** | 0 | **1** | 0 | 0 | 0 |

- MAB

| CC | RAO | RAI | RBO | RBI | SUB | ALO | PCI | PCO | CNT | MRI | RMI | RMO | IRI | IRO |
|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|
| 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |


- MBA

| CC | RAO | RAI | RBO | RBI | SUB | ALO | PCI | PCO | CNT | MRI | RMI | RMO | IRI | IRO |
|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|
| 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |

- NOP

| **CC** | **RAO** | **RAI** | **RBO** | **RBI** | **SUB** | **ALO** | **PCI** | **PCO** | **CNT** | **MRI** | **RMI** | **RMO** | **IRI** | **IRO** |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | **1** | 0 | 0 | 0 | 0 | 0 |

- JMP

| **CC** | **RAO** | **RAI** | **RBO** | **RBI** | **SUB** | **ALO** | **PCI** | **PCO** | **CNT** | **MRI** | **RMI** | **RMO** | **IRI** | **IRO** |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |


- CMP

| **CC** | **RAO** | **RAI** | **RBO** | **RBI** | **SUB** | **ALO** | **PCI** | **PCO** | **CNT** | **MRI** | **RMI** | **RMO** | **IRI** | **IRO** |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |

- ADD

| **CC** | **RAO** | **RAI** | **RBO** | **RBI** | **SUB** | **ALO** | **PCI** | **PCO** | **CNT** | **MRI** | **RMI** | **RMO** | **IRI** | **IRO** |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |

- SUB

| **CC** | **RAO** | **RAI** | **RBO** | **RBI** | **SUB** | **ALO** | **PCI** | **PCO** | **CNT** | **MRI** | **RMI** | **RMO** | **IRI** | **IRO** |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 

- HLT

| **CC** | **RAO** | **RAI** | **RBO** | **RBI** | **SUB** | **ALO** | **PCI** | **PCO** | **CNT** | **MRI** | **RMI** | **RMO** | **IRI** | **IRO** |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |

Sekarang baca kembali daste (jika belum ya baca lah) : 
https://learn.digilabdte.com/books/digital-sistem-design-psddsg/chapter/module-9-microprogramming

### A. Dari sini ubahlah code yang anda kerjakan dari yang tadinya merupakan FSM menjadi bentuk microprogrammingnya (25 pts)

ISI **TODO** : 

```vhdl
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity control_unit is
    port (
        CLK             : in std_logic;
        enable          : in std_logic;
        RST             : in std_logic;
        carry_flag      : in std_logic;
        zero_flag       : in std_logic;
        opcode          : in std_logic_vector(3 downto 0);
        control_signals : out std_logic_vector(13 downto 0) 
    );
end entity control_unit;

architecture rtl_classic_microprogram of control_unit is

    -- ### 1. Definisi Format Micro-Instruction ###
    
    constant C_CTRL_BITS : integer := 14; 
    constant C_SEQ_BITS  : integer := 2;  
    constant C_UCODE_WIDTH : integer := C_CTRL_BITS + C_SEQ_BITS; 
    
    -- Perintah sequencing
    constant SEQ_NEXT   : std_logic_vector(1 downto 0) := "00"; =
    constant SEQ_DECODE : std_logic_vector(1 downto 0) := "01"; =
    constant SEQ_FETCH  : std_logic_vector(1 downto 0) := "10"; =
    constant SEQ_HLT    : std_logic_vector(1 downto 0) := "11"; =

    -- ### 2. Control Store (ROM) ###

    subtype t_uAddress is unsigned(7 downto 0);
    type t_control_store is array(0 to 255) of std_logic_vector(C_UCODE_WIDTH - 1 downto 0);

    -- Helper function
    function to_ucode(
        ctrl : std_logic_vector(C_CTRL_BITS - 1 downto 0);
        seq  : std_logic_vector(C_SEQ_BITS - 1 downto 0)
    ) return std_logic_vector is
    begin
        return seq & ctrl;
    end function;

    -- Alamat untuk Fetch
    constant uADDR_FETCH1 : t_uAddress := x"00"; -- 0
    constant uADDR_FETCH2 : t_uAddress := x"01"; -- 1
    constant uADDR_FETCH3 : t_uAddress := x"02"; -- 2
    
    -- =============TODO: Konstanta Alamat Micro-Routine (Jarak 2) =============
    constant uADDR_NOP1 : t_uAddress := x"10"; -- 16
    constant uADDR_LDA1 : t_uAddress := x"12"; -- 18
    constant uADDR_STA1 : t_uAddress := x"14"; -- 20
    constant uADDR_ADD1 : t_uAddress := x"16"; -- 22
    constant uADDR_MAB1 : t_uAddress := x"18"; -- 24
    constant uADDR_LDB1 : t_uAddress := x"1A"; -- 26
    constant uADDR_STB1 : t_uAddress := x"1C"; -- 28
    constant uADDR_MBA1 : t_uAddress := x"1E"; -- 30
    constant uADDR_JMP1 : t_uAddress := x"20"; -- 32
    constant uADDR_CMP1 : t_uAddress := x"22"; -- 34
    constant uADDR_SUB1 : t_uAddress := x"24"; -- 36
    constant uADDR_HLT1 : t_uAddress := x"26"; -- 38
    -- =========================================================================

    -- Inisialisasi ROM
    function init_rom return t_control_store is
        variable rom : t_control_store := (others => (others => '0'));
        
        -- Sinyal Fetch (Sudah ada)
        constant C_FETCH1 : std_logic_vector(13 downto 0) := "00000001010000"; -- PCO, MRI
        constant C_FETCH2 : std_logic_vector(13 downto 0) := "00000000000110"; -- RMO, IRI
        constant C_FETCH3 : std_logic_vector(13 downto 0) := "00000000000110"; -- RMO, IRI (Decode wait)
        
        -- =============TODO: Konstanta Control Signals (14 bit) =============
        
        -- Common Signal (Memory Address Setup)
        constant C_MEM_SETUP : std_logic_vector(13 downto 0) := "00000000001001"; -- MRI, IRO
        
        -- Instructions
        constant C_NOP : std_logic_vector(13 downto 0) := "00000000100000"; -- CNT
        
        constant C_LDA_EXE : std_logic_vector(13 downto 0) := "01000000100100";
        constant C_STA_EXE : std_logic_vector(13 downto 0) := "10000000100010";
        
        constant C_LDB_EXE : std_logic_vector(13 downto 0) := "00010000100100"; 
        constant C_STB_EXE : std_logic_vector(13 downto 0) := "00100000100010"; 
        
        constant C_MAB : std_logic_vector(13 downto 0) := "10010000100000"; 
        constant C_MBA : std_logic_vector(13 downto 0) := "01100000100000"; 
        
        constant C_ADD : std_logic_vector(13 downto 0) := "01000100100000";
        constant C_SUB : std_logic_vector(13 downto 0) := "01001100100000"; 
        constant C_CMP : std_logic_vector(13 downto 0) := "00001000100000"; 
        
        constant C_JMP : std_logic_vector(13 downto 0) := "00000010000001"; 
        constant C_HLT : std_logic_vector(13 downto 0) := "00000000000000"; 
        -- ==================================================================

    begin
        rom(to_integer(uADDR_FETCH1)) := to_ucode(C_FETCH1, SEQ_NEXT);
        rom(to_integer(uADDR_FETCH2)) := to_ucode(C_FETCH2, SEQ_NEXT);
        rom(to_integer(uADDR_FETCH3)) := to_ucode(C_FETCH3, SEQ_DECODE);
        
        -- ===========TODO: Isi ROM Micro-routines =============
        
        -- NOP (Opcode 0000) - 1 Cycle
        rom(to_integer(uADDR_NOP1)) := to_ucode(C_NOP, SEQ_FETCH);

        -- LDA (Opcode 0001) - 2 Cycles
        rom(to_integer(uADDR_LDA1))   := to_ucode(C_MEM_SETUP, SEQ_NEXT);
        rom(to_integer(uADDR_LDA1)+1) := to_ucode(C_LDA_EXE, SEQ_FETCH);

        -- STA (Opcode 0010) - 2 Cycles
        rom(to_integer(uADDR_STA1))   := to_ucode(C_MEM_SETUP, SEQ_NEXT);
        rom(to_integer(uADDR_STA1)+1) := to_ucode(C_STA_EXE, SEQ_FETCH);

        -- ADD (Opcode 0011) - 1 Cycle
        rom(to_integer(uADDR_ADD1)) := to_ucode(C_ADD, SEQ_FETCH);

        -- MAB (Opcode 0100) - 1 Cycle
        rom(to_integer(uADDR_MAB1)) := to_ucode(C_MAB, SEQ_FETCH);

        -- LDB (Opcode 0101) - 2 Cycles
        rom(to_integer(uADDR_LDB1))   := to_ucode(C_MEM_SETUP, SEQ_NEXT);
        rom(to_integer(uADDR_LDB1)+1) := to_ucode(C_LDB_EXE, SEQ_FETCH);

        -- STB (Opcode 0110) - 2 Cycles
        rom(to_integer(uADDR_STB1))   := to_ucode(C_MEM_SETUP, SEQ_NEXT);
        rom(to_integer(uADDR_STB1)+1) := to_ucode(C_STB_EXE, SEQ_FETCH);

        -- MBA (Opcode 0111) - 1 Cycle
        rom(to_integer(uADDR_MBA1)) := to_ucode(C_MBA, SEQ_FETCH);

        -- JMP (Opcode 1000) - 1 Cycle
        rom(to_integer(uADDR_JMP1)) := to_ucode(C_JMP, SEQ_FETCH);

        -- CMP (Opcode 1001) - 1 Cycle
        rom(to_integer(uADDR_CMP1)) := to_ucode(C_CMP, SEQ_FETCH);

        -- SUB (Opcode 1100) - 1 Cycle
        rom(to_integer(uADDR_SUB1)) := to_ucode(C_SUB, SEQ_FETCH);

        -- HLT (Opcode 1111) - Infinite
        rom(to_integer(uADDR_HLT1)) := to_ucode(C_HLT, SEQ_HLT);

        return rom;
    end function;

    constant Control_Store : t_control_store := init_rom;

    -- ### 3. Sinyal Internal ###
    signal uPC     : t_uAddress := uADDR_FETCH1;
    signal Next_uPC : t_uAddress;
    signal uIR : std_logic_vector(C_UCODE_WIDTH - 1 downto 0);
    
begin

    -- ### PROSES 1: uPC Register ###
    uPC_REGISTER: process(CLK) is
    begin
        if enable = '1' and rising_edge(CLK) then
            if RST = '1' then
                uPC <= uADDR_FETCH1;
            else
                uPC <= Next_uPC;
            end if;
        end if;
    end process uPC_REGISTER;

    -- ### PROSES 2: Pembacaan ROM ###
    uIR <= Control_Store(to_integer(uPC));

    -- ### PROSES 3: Sequencer Logic ###
    SEQUENCER_LOGIC: process(uPC, uIR, opcode, carry_flag, zero_flag)
        variable seq_control : std_logic_vector(1 downto 0);
    begin
        seq_control := uIR(C_UCODE_WIDTH - 1 downto C_CTRL_BITS);
        
        -- Default
        Next_uPC <= uPC + 1;

        case seq_control is
            when SEQ_NEXT =>
                Next_uPC <= uPC + 1;
                
            when SEQ_FETCH =>
                Next_uPC <= uADDR_FETCH1;

            when SEQ_HLT =>
                Next_uPC <= uPC; 

            when SEQ_DECODE =>
                -- =============TODO: Implementasikan decoding opcode=============
                -- Mapping Opcode ke Alamat Awal Micro-Routine
                case opcode is
                    when "0000" => Next_uPC <= uADDR_NOP1;
                    when "0001" => Next_uPC <= uADDR_LDA1;
                    when "0010" => Next_uPC <= uADDR_STA1;
                    when "0011" => Next_uPC <= uADDR_ADD1;
                    when "0100" => Next_uPC <= uADDR_MAB1;
                    when "0101" => Next_uPC <= uADDR_LDB1;
                    when "0110" => Next_uPC <= uADDR_STB1;
                    when "0111" => Next_uPC <= uADDR_MBA1;
                    when "1000" => Next_uPC <= uADDR_JMP1;
                    when "1001" => Next_uPC <= uADDR_CMP1;
                    when "1100" => Next_uPC <= uADDR_SUB1;
                    when "1111" => Next_uPC <= uADDR_HLT1;
                    when others => Next_uPC <= uADDR_FETCH1;
                end case;
                -- ===============================================================
                
            when others =>
                Next_uPC <= uADDR_FETCH1;
        end case;
    end process SEQUENCER_LOGIC;

    -- ### PROSES 4: Output Logic ###
    control_signals <= uIR(13 downto 0);

end architecture rtl_classic_microprogram;
```

***Kalo bener harusnya hasilnya Begini :*** 
![image](https://hackmd.io/_uploads/rJUqY4zgbx.png)

#### Hasil dijalankan : 
![image](https://hackmd.io/_uploads/SyobfwtgZe.png)


### A. Jelaskan apa yang testbench tersebut lakukan dengan memakai control unit anda. Berikan cuplikan kodenya bagian mana yang melakukannya (HINT : liat di RAM di testbench) (tidak usah referensi) (20 pts)

Berdasarkan inisialisasi RAM pada testbench, program melakukan serangkaian operasi aritmatika sederhana. 

1. RAM[0] (LDA 8): Muat data dari RAM[8] (10) ke Register A. A = 10.
1. RAM[1] (LDB 9): Muat data dari RAM[9] (5) ke Register B. B = 5.
1. RAM[2] (ADD): Hitung A + B (10 + 5). A = 15.
1. RAM[3] (LDB 10): Muat data baru dari RAM[10] (3) ke Register B. B = 3.
1. RAM[4] (SUB): Hitung A - B (15 - 3). A = 12.
1. RAM[5] (HLT): Hentikan eksekusi program.

# BoNUS (0 poin)

### 1. Modul PSD siapa yang paling sulit (sebutkan aslabnya)
### 2. Apakah anda senang belajar PSD selama ini
PSD > OOP
### 3. Siapkah anda belajar assembly (teaser)
umu