Half & Quad Precision Floating Point Support

{%hackmd theme-dark %} This doc is just an attempt to get all our ducks in a row and put everything together with sources. Everything with a ✅ should probably have a source. Note that this doc isn't saying that we want to support everything with a checkmark, this is just a place to collect what might be possible. Platforms link: https://doc.rust-lang.org/nightly/rustc/platform-support.html Table should cover all T1 & T2-hosttools targets. Compat:[^l-fp][^g-fp][^g-hp][^c-fp] - `f128`: C++ `std::float128_t`, C `_Float128`, LLVM `fp128`, GCC `__float128` - `f16`: C++ `std::float16_t`, C `_Float16`, LLVM `half`, GCC `__fp16` - `f16b`: C++ `std::bfloat16_t`, LLVM `bfloat`, GCC `__bf16` - `f80`: C/C++ `long double`[^g-fp], LLVM `x86_fp80`, GCC `__float80` - `f64f64`: C/C++ `long double`[^g-fp], LLVM `ppc_fp128`, GCC `__ibm128`, called `double double` | Platform | f128 | f16 | f16b | f80 | f64f64 | c_longdouble | |-----------------------|--------------|------------------|-------------|--------------|--------------|--------------| | arm-\*-gnueabihf | ❌ | ⊛[^n6] | 🪣[^l-hp] | ❌ | ❌ | f64 | | armv7-\*-gnueabihf | ❌ | ⊛[^n6] | 🪣[^l-hp] | ❌ | ❌ | f64 | | aarch64-\*-!msvc | ❌ | ⊛[^n6] | 🪣[^l-hp] | ❌[^a-ep] | ❌ | f128 | | aarch64-\*-msvc | ❌ | ⊛[^n6] | 🪣[^l-hp] | ❌[^a-ep] | ❌ | f64[^m-fp] | | x86_32-\*-!msvc | 📃 | ❌ ⊛[^n-12] | ❌,🪣⊛[^n11] | ✅[^g-fp] | ❌ | f80[^n9] | | x86_32-\*-msvc | ❌ | ❌ ⊛[^n-12] | ❌ | ❌[^m-fp] | ❌ | f64[^m-fp] | | x86_64-\*-!msvc | 📃 | ❌ ⊛[^n-12] | ❌,🪣⊛[^n11] | ✅[^g-fp] | ❌ | f80[^n9] | | x86_64-\*-msvc | ❌ | ❌ ⊛[^n-12] | ❌ | ❌[^m-fp] | ❌ | f64[^m-fp] | | loongarch64-\*-gnu | 📗[^o-fp] | ❌[^o-fp]⊛[^n-12]| ❌[^o-fp] | ❌[^o-fp] | ❌[^o-fp] | f128 | | loongarch64-\*-softfl | 📗[^o-fp] | ❌[^o-fp]⊛[^n-12]| ❌[^o-fp] | ❌[^o-fp] | ❌[^o-fp] | f128 | | mips-\*-gnu | 📗 | ❌[^i-fp] 🪣⊛[^n8]| ❌[^i-fp] | ❌[^i-fp] | ❌[^i-fp] | f64[^n13] | | mipsel-\*-gnu | 📗 | ❌[^i-fp] 🪣⊛[^n8]| ❌[^i-fp] | ❌[^i-fp] | ❌[^i-fp] | f64[^n13] | | mips64-\*-gnuabi64 | 📗 | ❌[^i-fp] 🪣⊛[^n8]| ❌[^i-fp] | ❌[^i-fp] | ❌[^i-fp] | f128 | | mips64el-\*-gnuabi64 | 📗 | ❌[^i-fp] 🪣⊛[^n8]| ❌[^i-fp] | ❌[^i-fp] | ❌[^i-fp] | f128 | | powerpc-\*-gnu | ⊛[^n1] | ⊛[^n2] | ⊛[^n2] | ⊛[^n3] | 📗[^g-pp] | f64f64/f128[^n7] | | powerpc64-\*-gnu | ⊛[^n1] | ⊛[^n2] | ⊛[^n2] | ⊛[^n3] | 📗[^g-pp] | f64f64/f128[^n7] | | riscv64gc-\*-gnu | ⊛[^n4] | ⊛[^n5] | ❌ | ❌ | ❌ | f128 | | s390x-\*-gnu | ✅[^z-fp] | ❌[^z-fp]⊛[^n-12] | ❌[^z-fp] | ❌[^z-fp] | ❌[^z-fp] | f128 | - ✅: supported with hardware acceleration - 📗: supported with soft float, ABI defines type / operations for that type - 🪣: supported only as a storage format (f16b is a truncated f32), or some instruction support but no to-size FPU - 📃: Glibc 2.26+ provides a soft float implementation[^gl-rel] - 📒: Other soft float implementation used by GCC/LLVM (not glibc) - ⊛: sometimes supported or with features, see note - ❌: Not supported, type will not exist - ?: this needs double checking  [^n1]: Only supported with BFP128 feature, introduced with PowerISA v3.0[^p-pp] [^n2]: Only supported with VSX on PowerISA v3.1+ (conversions only)[^p-pp] or with SVP64 (full HW support)[^ls-hp] [^n3]: Some HW support with BFP128 feature -- supports emulating `f80` by using `f128` hardware in round-to-odd mode with `xsrqpxp` instruction that rounds to `f80` [^n4]: Only supported with Q extension[^r-qp] [^n5]: Only supported with Zfh or Zfhmin extensions for RISC-V according to [^r-hp]. For ARM the supproted arch are according to [^l-hp] [^n6]: BFP16 support introduced in ARMv8.2 for both 32-bit and 64-bit ARM[^a8-fp] [^n7]: Default to `f64f64` currently. The default will be `f128` once the transition finished according to [^g-fp] and [^g-pp-ts]. Can be switched to one of `f128`/`f64`/`f64f64` depends on compilers option according to [^g-pp] [^n8]: Only supported with MSA[^i-msa] extension, introduced with MIPS R5. [^n9]: Default to `f80`. The size of `f80` is `12` on x86_32. The size of `f80` is `16` on x86_64. Can be switched to one of `f128`/`f64`/`f80` depends on compilers option according to [^g-pp]. [^n10]: Note that IMB Z/Arch refers to 128-bit floats as "extended", not f80 (see PoE page 1-9[^z-fp]) [^n11]: BFP is supported as a storage format on x86 if SSE2 is available[^l-fp] [^n12]: LLVM does support 16-bit floats on all targets as a storage only format[^l-hp] [^n13]: O32 ABI has f64 as `longdouble`  [^m-fp]: https://learn.microsoft.com/en-us/cpp/cpp/fundamental-types-cpp?view=msvc-170#floating-point-types [^l-fp]: https://llvm.org/docs/LangRef.html#floating-point-types [^l-hp]: https://releases.llvm.org/16.0.0/tools/clang/docs/LanguageExtensions.html#half-precision-floating-point [^g-fp]: https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/Floating-Types.html [^g-hp]: https://gcc.gnu.org/onlinedocs/gcc/Half-Precision.html [^g-pp-ts]: https://fedoraproject.org/wiki/Changes/PPC64LE_Float128_Transition [^g-pp]: https://gcc.gnu.org/wiki/Ieee128PowerPC [^c-fp]: https://en.cppreference.com/w/cpp/types/floating-point [^a-ep]: https://developer.apple.com/documentation/swift/float80 [^p-pp]: https://files.openpower.foundation/s/dAYSdGzTfW4j2r2 [^ls-hp]: https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/ls005.xlen.mdwn;hb=5e573680771f7a041d93d394003d6f9f08177a98#l131 [^r-qp]: https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2023-05-23/src/q-st-ext.adoc [^r-hp]: https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2023-05-23/src/zfh.adoc [^gl-rel]: https://sourceware.org/git/?p=glibc.git;a=blob;f=NEWS;hb=81325b12b14c44887f1633a2c180a413afc2b504#l143 [^a8-fp]: https://developer.arm.com/documentation/den0024/a/Porting-to-A64/Data-types [^o-fp]: https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc [^i-fp]: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00083-2B-MIPS64INT-AFP-06.01.pdf [^i-msa]: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00868-1D-MSA64-AFP-01.12.pdf [^z-fp]: https://linux.mainframe.blog/zarchitecture-principles-of-operation/ SA22-7832-13