# A Survey of Computer Architecture Simulator Techniques and Tools
[LINK](https://ieeexplore.ieee.org/document/8718630)
## ABSTRACT
:::spoiler Detail of Abstract
- This paper reviews the fundamentals of different computer architecture simulation techniques.
- It also surveys many computer architecture simulators and classifies them into different groups based on their simulation models.
- Comparing computer architecture simulators with each other and validating their accuracy have been demanding tasks for architects.
- In addition to providing a survey of computer architecture simulation tools, we measured the experimental error of six contemporary computer architecture simulators:
- gem5
- MARSSx86
- Multi2Sim
- PTLsim
- Sniper
- ZSim.
- We also performed a detailed comparison of these simulators based on other features such as
- flexibility
- micro-architectural details.
:::
## Index terms
- Computer architecture simulators
- Simulation techniquesvalidation
- x86 simulators
- Simulators evaluation.
## 1. INTRODUCTION
- Computer architects use simulation to assess different design options, test new research ideas and analyze the performance/power consumption of different processor models.
- **Analytical models are not suitable** for evaluating architectural/microarchitectural designs and design variations as they produce inaccurate results **because of the huge amount of configurations and small details that can cause small variations in performance**.
- ==Simulation is considered to be the standard performance modeling method== [[1](https://ieeexplore.ieee.org/abstract/document/1220579)].

- In computer architecture, the main goal of simulation is
- to model new research ideas for parts of a computer system *(e.g. microprocessor, memory, IO devices)* or a complete computer system
- estimate the performance improvements and/or power consumption.
- evaluating, debugging and understanding the behavior of existing systems.

- Workloads that run on simulators can **be standard test programs, known as benchmarks**, which are run to assess the performance of a processor or a computer. ==The workload being simulated can also be an operating system (OS), sometimes referred as a guest OS==.

The interaction between a simulator and a host system is shown in Figure 1.

---
### Our major contributions in this paper are :
- Providing an **up-to-date survey** of computer architecture simulation techniques and simulators.
- **Categorizing, analyzing and comparing various computer architecture simulators**, which can help the community to understand the use-cases of different simulation tools.
- Providing **detailed characteristics** and **experimental error** comparison of six modern x86 computer architecture simulators :
- gem5 [[2](https://dl.acm.org/doi/10.1145/2024716.2024718)]
- Multi2sim [[3](https://ieeexplore.ieee.org/document/4384043)]
- MARSSx86 [[4](https://www.researchgate.net/profile/Wei-Chung-Hsu-3/publication/241626652_PQEMU_A_parallel_system_emulator_based_on_QEMU/links/00b495324de9fec616000000/PQEMU-A-parallel-system-emulator-based-on-QEMU.pdf#page=33)]
- PTLsim [[5](https://ieeexplore.ieee.org/document/4211019)]
- Sniper [[6](https://ieeexplore.ieee.org/abstract/document/6114398)]
- ZSim [[7](https://dl.acm.org/doi/10.1145/2508148.2485963)]
- Reviewing the most important challenges for architecture simulators and the solutions that have been proposed to resolve those issues.
- This survey is a more comprehensive and an updated survey **compared to previous existing surveys**, which either focused on
- teaching related simulators [8]–[11],
- memory simulators [12], [13], which use reference address traces.
- [14]evaluated the performance results of three different computer architecture simulators against each other.
- However, this study did not compare the simulators with real hardware runs.
- [15] discussed various pitfalls associated with the usage of architectural simulators.
- gem5
- GPGPUSim [16]
- McPAT [17]
- GPUWattch [18].
- Validation efforts for various simulators *(e.g. SimpleScalar, SMARTS, Microlib, gem5, Sniper, SiNUCA, Ramulator)* have also been published [19]–[25].
- These papers focus only on one simulator that is being validated and **usually do not include comparisons with related tools**.
- This survey is up-todate, which includes newer processor architecture simulators, and it is more detailed compared to previous surveys.
- In order to accelerate the process of simulation, The paper also discusses few of **the commonly used sampling methods associated with simulating computer architecture components**.
- For the accuracy of simulation results. We briefly explore different existing simulator validation approaches.
- This work compares the experimental error of six x86 simulators with hardware runs and provides the relative performance of the simulators when changing some microarchitectural configurations.
- Finally, we pinpoint some causes of inaccuracies in the simulation results that we observed.
### Scope of the paper:
1. We limit the scope of the paper to review in details computer architectural and microarchitectural simulators and simulation models of processors.
2. The paper **mentions some uncore and accelerator simulators**. It does not survey in details standalone specialized simulators for mircorachictectrual structures or uncore components; however, it does mention detailed microarchitectural or uncore simulations as features of those full computer architectural/microarchitectural simulators. It also discusses those full simulators that can also simulate accelerators or can be attached to accelerator simulators.
3. To limit the scope, the paper does **not cover in details specific implementation limitations**, such as handling target multi-threading.

## 2. CLASSIFICATION OF SIMULATORS
- Simulators can be classified into various groups on the basis of three most important factors:
- detail of simulation
- scope of the target
- input to the simulator
- This classification is **not mutually exclusive**.
- Some simulators are classified based on certain aspects or specializations.

### A. CLASSIFYING SIMULATORS BASED ON THE DETAIL OF SIMULATION
#### 1) FUNCTIONAL SIMULATORS
#### 2) TIMING SIMULATORS
##### Cycle-level Simulators
##### Event-driven Simulators
##### Interval Simulators
#### 3) INTEGRATED TIMING AND FUNCTIONAL SIMULATORS
##### Timing-directed Simulators
##### Functional-First Simulators
##### Timing-First Simulators

### B. CLASSIFYING SIMULATORS BASED ON THE SCOPE OF THE TARGET
#### 1) FULL-SYSTEM SIMULATOR
#### 2) APPLICATION LEVEL/USER MODE SIMULATOR

### C. CLASSIFYING SIMULATORS BASED ON THE INPUT TO THE SIMULATOR
#### 1) TRACE-DRIVEN SIMULATORS
#### 2) EXECUTION-DRIVEN SIMULATORS

### D. OTHER SIMULATOR CATEGORIES
#### 1) MULTIPROCESSOR/MULTICORE SIMULATORS
#### 2) ENERGY AND POWER SIMULATORS
#### 3) SPECIALIZED/ACCELERATOR SIMULATORS
#### 4) MODULAR SIMULATORS

graph TD
bd>BASED ON THE DETAIL]-->f(FUNCTIONAL SIMULATORS)
bd-->t(TIMING SIMULATORS)
bd-->i(INTEGRATED TIMING AND FUNCTIONAL SIMULATORS)
t-->Cycle-level
t-->Event-driven
t-->Interval
i--->Timing-directed
i--->Functional-First
i--->Timing-First

graph TD
bc>BASED ON THE SCOPE OF THE TARGET]
bc-->FULL-SYSTEM
bc-->APPLICATION_LEVEL/USER_MODE

graph TD
bi>BASED ON THE INPUT TO]
bi-->TRACE-DRIVEN
bi-->EXECUTION-DRIVEN

graph TD
ot>OTHER]
ot-->MULTIPROCESSOR/MULTICORE
ot-->ENERGY_AND_POWER
ot--->SPECIALIZED/ACCELERATOR
ot--->MODULAR

graph TD
c>CHALLENGES OF SIMULATIO]
c-->s(slow_simulation)
s-->s1[[sampled]]
s-->s2[[statisical]]
s-->s3[[parallel_simulation]]
s-->s4[[FPGA_acelerated_simulation]]
s1-->sp1[[statistical_sampling]]
s1-->sp2[[targeted_sampling]]
c-->p(poor accuracy)
p-->p1(Modeling errors)
p-->p2(specification errors)
p-->p3(abstraction errors)