# The Design of Half_Adder, Full_Adder and Ripple_Adder -數位邏輯技術

## Half_Adder

* Truth Table of Half_Adder


* Boolean Function of Half_Adder
* $S=x \oplus y$
* $C=x \cdot y$

* Block Diagram of Half_Adder


* VHDL of Half_Adder

    library ieee;
    use ieee.std_logic_1164.all;

    entity half_adder is
        port
        (
            x: in std_logic;
            y: in std_logic;
            s: out std_logic;
            c: out std_logic
        );
    END half_adder;

    ARCHITECTURE behavioral of half_adder is
    begin 
    c <= x xor y;
    s <= x and y;
    end behavioral;

## Full_Adder
* Full_Adder can be realised with a combination of two Half_Adders
* Truth Table of Full_Adder


* Block Diagram of Full_Adder


* VHDL of Full_Adder

    library ieee;
    use ieee.std_logic_1164.all;

    entity full_adder is
        port
        (
            a: in std_logic;
            b: in std_logic;
            ci: in std_logic;
            sum: out std_logic;
            co: out std_logic		
        );
    end entity;

    architecture behavioral of full_adder is
        signal sum1, sum2, carry1, carry2: std_logic;

        component half_adder is
            port 
            (
                x: in std_logic; 
                y: in std_logic;
                s: out std_logic;
                c: out std_logic
        );
        end component;

    begin
        half_adder1: half_adder
            port map (
                    x => a,
                    y => b,
                    s => sum1,
                    c => carry1
                );

        half_adder2: half_adder
            port map(
                x => sum1,
                y => ci,
                s => sum2,
                c => carry2

            );
        sum <= sum2;
        co <= carry1 or carry2 ;
    end behavioral;
	 

## 4_bits_Ripple_Adder

* Block Diagram


* VHDL of 4_bits_Ripple_Adder

    library ieee;
    use ieee.std_logic_1164.all;

    entity ripple_adder is
        port
            (
                a0: in std_logic;
                a1: in std_logic;
                a2: in std_logic;
                a3: in std_logic;

                b0: in std_logic;
                b1: in std_logic;
                b2: in std_logic;
                b3: in std_logic;

                c_initial: in std_logic;
                c_final: out std_logic;

                s0: out std_logic;
                s1: out std_logic;
                s2: out std_logic;
                s3: out std_logic
            );
    end entity;

    architecture behavioral of ripple_adder is
        signal carry0, carry1, carry2: std_logic;
        component full_adder is
            port 
            (
                a: in std_logic;
                b: in std_logic;
                ci: in std_logic;
                sum: out std_logic;
                co: out std_logic		
            );
        end component;

    begin
        full_adder0: full_adder
            port map
            (
                a => a0,
                b => b0,
                ci => c_initial,
                co => carry0,
                sum => s0
            );

        full_adder1: full_adder
            port map
            (
                a => a1,
                b => b1,
                ci => carry0,
                co => carry1,
                sum => s1
            );

        full_adder2: full_adder
            port map
            (
                a => a2,
                b => b2,
                ci => carry1,
                co => carry2,
                sum => s2
            );

        full_adder3: full_adder
            port map
            (
                a => a3,
                b => b3,
                ci => carry2,
                co => c_final,
                sum => s3
            );
    end behavioral;

## Source Code Download
[Download](https://github.com/Shih-Jiun-Lin/The-Design-of-Adders)