# Assignment-4
* ## Ternary Logic Operations
* ### Arithmetic-
arithmatic operations will be similar to that being done in
binary system.
Instead of bits, we will use trits.
Also,The number representation will be changed .
for 2 trits,
0=00
1=01
2=02
3=10
4=11
5=12
6=20
7=21
8=22
* ### logical-
operations between 0 and 1 will be similar to that being done
in binary system.
we will assume 2 to be an unknown bit(just like a qubit which can be either 0 or 1) whereas 0 and 1 are false
and true respectively
0 && 2=0
1 && 2=2
2 && 2=2
0 || 2=2
1 || 1=1
2 || 2=2
!2=2

* ## Instruction Encoding
As we are use ternary system we can accomodate larger
range of instructions opcode,operands,registers in little bit architecture.

we can add many different kind of instructions like cnt1 will count number
of 1's in the number stored i the register or cnt0 or cnt2 .

So, I will prefer to go with RISC-V instruction format with many
additions in all type of(.i.e R-type,I-type,S-type,B-type,U-type,J-type)
instructions.

* ## Modified Ternary Pipeline Architecture with Unknown Bit

#### Instruction Fetch:
- Fetch ternary instructions from memory, decoding ternary opcode encodings.
- Identify instructions with the unknown bit, marking them for special handling.

#### Operand Fetch:
- Expand operand fetch to handle ternary operands with the unknown bit.
- Implement logic to handle uncertain operands by duplicating paths for both possible values (0 or 1).

#### Execution Units:
- Modify execution units to accommodate ternary operands with the unknown bit.
- Implement logic to perform operations considering both possible states of the unknown bit.

#### Memory Access:
- Adjust memory access to handle ternary memory addresses with the unknown bit.
- Develop mechanisms for accessing memory locations with uncertain addresses, possibly via speculative execution or parallel accesses.

#### Write Back:
- Adapt write-back to handle ternary results with the unknown bit.
- Implement logic to store results considering both possible states of the unknown bit.

#### Pipeline Modifications:
- Increase pipeline width or add stages to handle uncertainty from the unknown bit effectively.
- Develop mechanisms for handling hazards and resolving conflicts arising from uncertainty.

#### Branch Prediction:
- Enhance branch prediction to account for the unknown bit's uncertainty in ternary branch instructions.
- Develop strategies for predicting branch outcomes considering both possible states of the unknown bit.

### Benefits:
1. **Robust Handling of Uncertainty**:
- Customized pipeline stages handle the unknown bit's uncertainty for robust processing.
2. **Flexible Execution**:
- The architecture accommodates uncertainty in operands and memory addresses, allowing for flexible execution.
3. **Improved Reliability**:
- Considering both possible states of the unknown bit enables more informed decisions, leading to improved reliability.

* ### Ternary Addressing System: Ternary Address Translation Table (TATT)

#### Concept:
Introduce a novel way to implement a ternary addressing system using a Ternary Address Translation Table (TATT), which efficiently maps ternary addresses to physical memory locations.

#### Design Overview:
1. **Ternary Address Encoding**:
- Encode memory addresses using ternary digits (trits), allowing each address to represent three states (0, 1, 2).

2. **Ternary Address Translation Table (TATT)**:
- Develop a specialized table, the Ternary Address Translation Table (TATT), to translate ternary addresses to physical memory locations.
- The TATT contains entries that map ternary addresses to corresponding physical memory addresses.

3. **Hashing and Indexing**:
- Implement a hashing function to efficiently index into the TATT based on ternary address values.
- Use hash values derived from ternary address bits to locate corresponding entries in the TATT.

4. **Collision Resolution**:
- Employ collision resolution techniques to handle hash collisions and ensure accurate ternary address translation.
- Strategies such as chaining or open addressing can be utilized to resolve collisions and maintain TATT integrity.

5. **Dynamic Address Mapping**:
- Design the TATT to support dynamic address mapping, allowing for efficient allocation and deallocation of memory resources.
- Implement mechanisms for updating TATT entries dynamically as memory allocation changes over time.

6. **Efficient Lookup and Access**:
- Optimize TATT lookup operations for fast and efficient ternary address translation.
- Utilize caching mechanisms or associative memory structures to accelerate TATT access and minimize latency.

#### Benefits:
1. **Scalability and Flexibility**:
- The TATT architecture supports a scalable and flexible ternary addressing system, accommodating a wide range of memory sizes and configurations.
2. **Efficient Address Translation**:
- TATT enables efficient ternary address translation, minimizing overhead and latency associated with memory access.
3. **Dynamic Memory Management**:
- TATT facilitates dynamic memory management, allowing for adaptive allocation of memory resources based on application requirements.
4. **Collision Resolution**:
- Incorporating collision resolution techniques ensures robustness and accuracy in ternary address translation, maintaining data integrity.

### Efficient Exploitation of Unknown Bit:
Develop specialized memory access strategies that exploit the uncertainty of the unknown bit to optimize memory access patterns.
Like,whenever first bit of instruction is 2,go into a dynamic mode.
### Adaptive Hashing and Indexing:
Develop adaptive hashing algorithms that leverage the unknown bit to dynamically adjust hash functions based on the address uncertainty.
Use ternary address bits, including the unknown bit, to compute hash values and index into the TATT.