---
# System prepended metadata

title: lab sequential -- serial2parallel
tags: [lab sequential, serial2parallel]

---

# lab sequential -- serial2parallel

comparing resource
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- HLS
![](https://hackmd.io/_uploads/ByeDoHIo6h.png)

- Verilog
![](https://hackmd.io/_uploads/Bknnr8ja2.png)

comparing timing
---
- HLS
  - timing constraint
  ![](https://hackmd.io/_uploads/Hys3LIiT2.png)

  - timing report
  ![](https://hackmd.io/_uploads/rJ5mD8oan.png)


- Verilog
  - timing constraint
  ![](https://hackmd.io/_uploads/H1vEv8ip2.png)
  - timing report
  ![](https://hackmd.io/_uploads/rJVSwUsah.png)

comparing waveform
---
- HLS
![](https://hackmd.io/_uploads/HJcTwUjTh.png)

- Verilog
![](https://hackmd.io/_uploads/BkwAPUi6n.png)

key point
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1. It can be seen that the resource usage is less when writing in Verilog, and the number of flip-flops used can be accurately assessed through the Verilog code. This is unlike HLS, where it's difficult to directly determine the flip-flop usage from the HLS code.
2. It can be observed that the logic delay in the HLS version is greater than that in the Verilog version. Therefore, HLS WNS < Verilog WNS, and HLS WHS > Verilog WHS.
3. WNS stands for worst setup time slack, which indicates how much time is remaining until the next positive edge after the computation is complete, in the worst-case scenario.
4. WHS stands for worst hold time slack, which represents how long the value will hold during the positive edge in the worst-case scenario.

###### tags: `serial2parallel` `lab sequential`