# Lab combination -- parity generator

## HLS

c simulation
---

c synthesis
---
- report
- resource(predicted in vitis_hls)

co simulation
---
- co simulation pass

- waveform

block diagram
---
- block diagram

- synthesis success

## Verilog

Verilog code
---
- in github folder

Verilog testbench
---
- in github folder

simulation
---

## Compare
resource compare
---
- HLS

- Verilog

resouce utilization is same

key point
---
1. During testing, we will use the golden model calculated by software to compare with the results calculated by hardware.
2. In the Verilog testbench, it is necessary to add delays appropriately.
3. In Vitis HLS, in order to view the RTL waveform, co-simulation must be successfully completed.

###### tags: `parity generator` `lab combination`