# 數位電路學習資源

[Designing DNN Accelerators](https://inst.eecs.berkeley.edu/~eecs151/sp23/files/EECS251Leture-JennyHuang_2021.pdf)

[ELEC 502 Advanced Topics in VLSI: Deep Learning slide](https://people.ece.ubc.ca/~bradq/)

[Exploiting Sparsity](https://people.ece.ubc.ca/bradq/ELEC502Slides/ELEC502-Part19-ExploitingSparsity.pdf)

[張添烜老師 - 深度學習的模型壓縮與加速 Model Compression and Acceleration](https://youtube.com/playlist?list=PLj6E8qlqmkFv3cCjjX2SA1D4FJ9fadDij)

**Hardware-Software Codesign notes**

[Hardware-Software Codesign Course Notes](https://www.cs.ccu.edu.tw/~pahsiung/courses/codesign/notes/slides.html)

[
Scalable and Modularized RTL Compilation of Convolutional Neural Networks onto FPGA](https://fpl2016.org/slides/S5b_1.pdf)

B站

[](https://www.bilibili.com/medialist/detail/ml968018726?type=1)

[验证码_哔哩哔哩](https://search.bilibili.com/all?vt=54692939&keyword=数字集成电路设计&from_source=webtop_search&spm_id_from=333.824&order=click)

****Hardware for Machine Learning****

[Hardware for Machine Learning, Spring 2021](https://inst.eecs.berkeley.edu//~ee290-2/sp21/#resources)

### from 別人的hackmd

[Digital IC Design - HackMD](https://hackmd.io/@derek8955/BkK2Nb5Jo)

## 開發工具(FPGA)

vivado: 寫電路

modelsim: 看波形

## Verilog 學習

[](http://www.ee.ncu.edu.tw/~jfli/vlsidi/lecture/VerilogCoding-2009.pdf)

[Welcome To Verilog Page](https://www.asic-world.com/verilog/index.html)

[](https://d1.amobbs.com/bbs_upload782111/files_25/ourdev_528029.pdf)

[Verilog](https://www.chipverify.com/verilog/verilog-tutorial)

[](https://www.eecs.umich.edu/courses/eecs270/270lab/270_docs/Advanced_Verilog.pdf)

[牛客网在线编程_编程学习|练习题_数据结构|系统设计题库](https://www.nowcoder.com/exam/oj?page=1&tab=Verilog篇&topicId=301)

[HDLBits](https://hdlbits.01xz.net/wiki/Main_Page)

[Verilog 從放棄到有趣 :: 2018 iT 邦幫忙鐵人賽](https://ithelp.ithome.com.tw/users/20107543/ironman/1492?page=1)

[D J Greaves - Undergraduate Teaching](https://www.cl.cam.ac.uk/~djg11/teaching.html)

[](https://www.cl.cam.ac.uk/~djg11/teaching/learners.pdf)

[](https://www.cl.cam.ac.uk/~djg11/teaching/slides.pdf)

[](https://www.cl.cam.ac.uk/~djg11/teaching/shd.pdf)

[](https://www.cl.cam.ac.uk/teaching/0910/SysOnChip/notes0910.pdf)

[Design Compiler综合操作](https://verdvana.cn/_posts/2020-03-15-Design-Compiler%E7%BB%BC%E5%90%88%E6%93%8D%E4%BD%9C/)

[](http://www.ee.ncu.edu.tw/~jfli/vlsidi/lecture/VerilogCoding)

## Good tutorial youtube channel

[Adi Teman](https://www.youtube.com/c/AdiTeman/featured)

## VLSI course

[Digital VLSI Design](https://www.eng.biu.ac.il/temanad/digital-vlsi-design/)

[Index of /~jfli/vlsi21/lecture](http://www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/)

[Welcome to VLSI Information Processing Research Lab](http://viplab.cs.nctu.edu.tw/teaching.php)

## Gated clock

[](https://classes.engineering.wustl.edu/ese461/Lecture/week12b.pdf)

### **NeuroSim tutorial**

[https://www.dropbox.com/s/a5oi04d1r79g4qt/20210917-NeuroSim.mp4?dl=0](https://www.dropbox.com/s/a5oi04d1r79g4qt/20210917-NeuroSim.mp4?dl=0)

model compression

[深度学习网络模型压缩剪枝详细分析](https://zhuanlan.zhihu.com/p/130645948)

### ****Tutorial on Hardware Accelerators for Deep Neural Networks****

[Tutorial on Hardware Accelerators for Deep Neural Networks](http://eyeriss.mit.edu/tutorial.html)

[dblp: computer science bibliography](https://dblp.org/)

### 分析工具

[Timeloop/Accelergy Tutorial](http://accelergy.mit.edu/tutorial.html)

[如何對比評價各種深度神經網路硬體？不妨給它們跑個分_矽說 - 微文庫](https://www.gushiciku.cn/dc_tw/101585013)

### Verdi

vcs -full64 -R -debug_access+all +v2k +memcbk

[Verdi /nWave看波形的基本操作小结_verdi看波形_丸子炖白菜的博客-CSDN博客](https://blog.csdn.net/eyeloveuv/article/details/79287668)

**dump fsdb waveform**

$fsdbDumpfile(”wave.fsdb”);

$fsdbDumpvars(testbenchname, “+all”); // dump all variable

**display FSM name in verdi**

verdi toolbar: choose tools→Extract Interactive FSM

[[Tool] Verdi 用法（dump waveform）_lbt_dvshare的博客-CSDN博客](https://blog.csdn.net/lbt_dvshare/article/details/86604379)

[芯片EDA技术席老师的个人空间-芯片EDA技术席老师个人主页-哔哩哔哩视频](https://space.bilibili.com/627172006/channel/collectiondetail?sid=757549)

[Synopsys IC Design Workshop](https://webinars.synopsys.com.tw/icworkshop/VideoDetail?id=125)

### Design compiler

[](http://archive.eclass.uth.gr/eclass/modules/document/file.php/MHX303/Documentation/dcug.pdf)

[數位電路設計](https://timsnote.wordpress.com/digital-ic-design/)

[](https://picture.iczhiku.com/resource/eetop/shkedggoGHzkAmNC.pdf)

Design Compiler® Register Retiming Reference Manual

[](http://www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/dc.pdf)

[](https://s2.smu.edu/~manikas/CAD_Tools/SDC/lab2/lab2_synopsys_dc.pdf)

good course slide

[VLSI Design Tutorials Using](https://www.eng.auburn.edu/~nelson/courses/elec5250_6250/)

## Innovus

sdc

[土豆土豆我是番茄 - 知乎](https://www.zhihu.com/people/di-di-di-53-28-61/posts)

[](https://limsk.ece.gatech.edu/course/ece6133/lab/innovus.pdf)

[Timing Analysis in Gate-Level Simulation (auburn.edu)](https://www.eng.auburn.edu/~nelson/courses/elec5250_6250/slides/ASIC%20Layout_2%20%20Digital%20Innovus.pdf)

[](https://eecs.wsu.edu/~daehyun/teaching/2020_EE434/Labs/tutorial-innovus.pdf)

[ECE 5745 Tutorial 5: Synopsys/Cadence ASIC Tools](https://cornell-ece5745.github.io/ece5745-tut5-asic-tools/)

[](https://s2.smu.edu/~manikas/CAD_Tools/CPR/lib/Innovus_PR_Tutorial2019Feb.pdf)

[innovus1809期](https://www.youtube.com/playlist?list=PL40HX6x4OOCUcS4p0s1cNX00DatmZD8au)

[](https://www.eng.biu.ac.il/temanad/files/2019/01/Lecture-9-Routing.pdf)

### 一些語法:

[Innovus流程（1）-init和FP](https://zhuanlan.zhihu.com/p/579681773)

[Innovus流程（2）-Place](https://zhuanlan.zhihu.com/p/579914676)

[Innovus流程（3）-CTS](https://zhuanlan.zhihu.com/p/580054919)

[Innovus流程（4）-Route和ECO](https://zhuanlan.zhihu.com/p/580275898)

### 如果 timing 沒過，可以設定cppr

定义：CPPR(CRPR)，Clock Path Pessimism Removal(Clock Reconvergence Pessimism Removal)，中文名“共同路径悲观去除”。它的作用是去除clock common path上的悲观量。

setAnalysisMode語法

setAnalysisMode [-help] [-reset] [-analysisType {single|bcwc|onChipVariation}] [-asyncChecks {async|noAsync|asyncOnly}]
[-caseAnalysis {true|false}] [-checkType {setup|hold}] [-clkNetsMarking {beforeConstProp|afterConstProp}]
[-clkSrcPath {true|false}] [-clockGatingCheck {true|false}]
[-clockPropagation {sdcControl|forcedIdeal|autoDetectClockTree}] [-cppr {both|none|setup|hold}]
[-enableMultipleDriveNet {true|false}] [-honorActiveLogicView {true|false}] [-honorClockDomains {true|false}]
[-log {true|false}] [-propSlew {true|false}] [-sequentialConstProp {true|false}] [-skew {true|false}]
[-timeBorrowing {true|false}] [-timingEngine {statistical|static}] [-timingSelfLoopsNoSkew {true|false}]
[-usefulSkew {true|false}] [-useOutputPinCap {true|false}] [-warn {true|false}] [-socv {true|false} | -aocv {true|false}]

setAnalysisMode -cppr {both none setup hold}

EX: setAnalysisMode -cppr hold

## Hold time 解決: 將Max density 調高(0.95 → 0.99)


setOptMode -effort high -powerEffort none -leakageToDynamicRatio 1 -reclaimArea true -simplifyNetlist true -allEndPoints false -setupTargetSlack 0 -holdTargetSlack 0 -maxDensity 0.99 -drcMargin 0 -usefulSkew true

## Verdi

[Verdi使用总结](https://www.wenhui.space/docs/07-ic-verify/tools/verdi_userguide/)

[Verdi 简单使用](https://www.skfwe.cn/p/verdi-简单使用/)

## Low power design

[什麼是低功耗設計？](https://www.synopsys.com/zh-tw/taiwan/blog/what-is-low-power-design.html)

[低功耗验证_Holden_Liu的博客-CSDN博客](https://blog.csdn.net/holden_liu/category_11162521.html)