# **VLSI -- logic effort**

[本文章感謝派網Pionex贊助](https://www.pionex.com/zh-TW/signUp?r=3uU7AXmq)
*logic effort :
(1) https://www.youtube.com/watch?v=3dakoUNe6yE&ab_channel=IITRoorkeeJuly2018
(2) https://www.youtube.com/watch?v=6599js1pMUs&abchannel=IITRoorkeeJuly2018*
(3) https://www.youtube.com/watch?v=KJr4xPWT1ao&ab_channel=IITRoorkeeJuly2018


::: success
parasitic delay 寄生電容產生的延遲
g 定義好的(inverter為1)
h = Cout/Cin
:::
::: success
logic effort 公式
:::
::: success
logic effort g = 1 (one input inverter)
parsitic delay p = 1 (inverter)
Cout/Cin h = 4 (1 inveter in 4 inverter out)
d = f + p = g*h + p = 1x4 + 1 = 5
:::
::: success
logic effort g = (2n+1)/3 = 9/3 (four input nor gate)
parsitic delay p = np = 4 (four input nor gate)
Cout/Cin h = 10 (1 nor gate in 10 nor gate out)
d = f + p = 9/3*10 + 4 = 34
:::

::: info
多級
:::