# Lab 8
**Name:** **G.NISHCHITH**
**Roll No.:** **CS22B021**

---
## Question 1
Given to write verilog code for full adder by using two half adders

module fulladder(sum,cout,a,b,c);
    input a,b,c;
    output sum,cout;
    wire w1,w2,s;
    halfadder h1(w1,w2,a,b);
    halfadder h2(sum,s,w1,c);
    assign cout = w2 | s;
endmodule


module halfadder(sum,cout,a,b);
input a,b;
output sum,cout;
assign sum=a^b;
assign cout=a&b;
endmodule
    

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//Test Bench

module testbench;
    reg a,b,c;
    wire sum,cout;
    fulladder out(.sum(sum),.cout(cout),.a(a),.b(b),.c(c));
    initial
        begin
            a=0;b=0;c=0; #10;
            a=0;b=0;c=1; #10;
            a=0;b=1;c=0; #10;
            a=0;b=1;c=1; #10;
            a=1;b=0;c=0; #10;
            a=1;b=0;c=1; #10;
            a=1;b=1;c=0; #10;
            a=1;b=1;c=1; #10;
        end
endmodule

Test Case:

---
## Question 2
Given to write verilog code 4-bit Ripple Carry Adder

module ripple_carryadder(sum,cout,a,b,c);
    input [3:0]a,b;
    input c;
    output [3:0] sum;
    output cout;
    wire w1,w2,w3;
    fulladder f1(sum[0],w1,a[0],b[0],c);
    fulladder f2(sum[1],w2,a[1],b[1],w1);
    fulladder f3(sum[2],w3,a[2],b[2],w2);
    fulladder f4(sum[3],cout,a[3],b[3],w3);
endmodule



module fulladder(sum,cout,a,b,c);
    input a,b,c;
    output sum,cout;
    assign sum = a^b^c;
    assign cout = (a&b) | (b&c) | (c&a);
endmodule


-------------

//testbench
module testbench;
    reg [3:0] a,b;
    reg c;
    wire [3:0] sum;
    wire cout;
    
    ripple_carryadder out(.sum(sum),.cout(cout),.a(a),.b(b),.c(c));
    
    initial
        begin
        a = 4'b0101; b = 4'b0011; c = 0; #10;
        a = 4'b1100; b = 4'b1100; c = 0; #10;    
        a = 4'b1111; b = 4'b0001; c = 1; #10;
        a = 4'b0010; b = 4'b1010; c = 1; #10; 
        end
endmodule

Testcase

---
## Question 3
Given to design 2:1 mux by structural modeling

module mux2to1(out,a,b,s);
    input a,b,s;
    output out;
    wire w1,w2,sb;
    not n(sb,s);
    and a1(w1,a,sb);
    and a2(w2,b,s);
    or o(out,w1,w2);
endmodule
    
-----------
//testbench

module testbench;
    reg a,b,s;
    wire out;
    mux2to1(.out(out),.a(a),.b(b),.s(s));
    initial
    begin
        a=0;b=0;s=0; #10;
        a=0;b=0;s=1; #10;
        a=0;b=1;s=0; #10;
        a=0;b=1;s=1; #10;
        a=1;b=0;s=0; #10;
        a=1;b=0;s=1; #10;
        a=1;b=1;s=0; #10;
        a=1;b=1;s=1; #10;
    end
endmodule
        

Testcase