# Lab 9
**Name:** **G.NISHCHITH**
**Roll No.:** **CS22B021**

---
## Question 1
Given to write verilog code for ALU which takes two inputs and gives output.

module alu(result,opcode,a,b);
    input [3:0] a,b;
    input [1:0] opcode;
    output [3:0] result;
    always@(a or b or opcode)
        begin
            case(opcode)
                2'b00: result = a + b;
                2'b01: result = a - b;
                2'b10: result = a & b;
                2'b11: result = a | b;
                default: result = 4'b0000;
            endcase
        end
endmodule

module mux4to1(out,in0,in1,in2,in3,sel);
    input [3:0] in0,in1,in2,in3;
    input [1:0] sel;
    output [3:0] out;
    always@(in0 or in1 or in2 or in3 or sel)
        begin
            case(sel)
                2'b00: out = in0;
                2'b01: out = in1;
                2'b10: out = in2;
                2'b11: out = in3;
                default: out = 4'b0000;
            endcase
        end
endmodule

---------------------

//testbench

module testbench;
    reg [3:0] a,b;
    reg [1:0] opcode;
    wire [3:0] result,out;
    
    alu a(.result(result),.opcode(opcode),.a(a),.b(b));
    
    mux4to1 m(.out(out),.in0(4'b0000),.in1(4'b0000),.in2(4'b0000),.in3(result),.sel(opcode));
    
    initial
        begin
            a = 4'b0101; b = 4'b0011; opcode = 2'b00; #10;
            a = 4'b0110; b = 4'b0010; opcode = 2'b01; #10;
            a = 4'b1100; b = 4'b1010; opcode = 2'b10; #10;
            a = 4'b0011; b = 4'b0110; opcode = 2'b11; #10;
        end
endmodule
            


---
# Question 2
Given to write verilog code simple 8-bit processor capable of load and store operation.

module simple_processor(input [7:0] instructions);
    reg [7:0] memory [255:0];
    reg [7:0] reg_file [15:0];
    reg opcode;
    reg [1:0] destination;
    reg [2:0] offset;
    reg [1:0] source;
    
    always@(*)
        begin
            opcode = instructions[7];
            destination = instructions[6:5];
            offset = instructions[4:2];
            source = instructions[1:0];
        end
    always@(*)
        begin
            if(opcode == 1'b0)
                begin
                    reg_file[destination] <= memory[reg_file[source]+offset];
                end
        end
    always@(*)
        begin
            if(opcode=1'b1)
                begin
                    memory[reg_file[source]+offset] <= reg_file[destination];
                end
        end
endmodule


---
## Question 3:

#include <stdio.h>

int main(){
    int x = 7;
    printf("%d\n",x);
    return 0;
}

**Total number of Instructions: 140380.**