---
# System prepended metadata

title: 'Lab 10 ,11'

---

**Name: G.Nishchith**
**Roll No: CS22B021**

ALU
---

Give to implement the Single cycle processor in Verilog.

``` verilog=

module alu(result,a,b,opcode);
    input [31:0] a;
    input [31:0] b;
    input [6:0] opcode;
    output reg [31:0] result;
    
    wire [31:0] addr,subr,xorr,orr,andr,sllr,srlr,srar,sltr,sltur,lwr1,lwr2;
    
    add_r q1(.y(addr),.a(a),.b(b));
    sub_r q2(.y(subr),.a(a),.b(b));
    or_r q3(.y(orr),.a(a),.b(b));
    and_r q4(.y(andr),.a(a),.b(b));
    xor_r q5(.y(xorr),.a(a),.b(b));
    sll_r q6(.y(sllr),.a(a),.b(b));
    srl_r q7(.y(srlr),.a(a),.b(b));
    sra_r q9(.y(srar),.a(a),.b(b));
    slt_r q10(.y(sltr),.a(a),.b(b));
    sltu_r q11(.y(sltur),.a(a),.b(b));
    lw_r q12(.y(lwr1),.rs(a),.offset(b));
    lw_r q13(.y(lwr2),.rs(a),.offset(b));
    
    always @(*)
        begin
            case(opcode)
                7'b0000000: result = addr; // Add
                7'b0000001: result = subr; // Subtract
                7'b0000010: result = xorr; // XOR
                7'b0000011: result = orr; // OR
                7'b0000100: result = andr; // AND
                7'b0000101: result = sllr; // Shift Left Logical
                7'b0000110: result = srlr; // Shift Right Logical
                7'b0000111: result = srar; // Shift Right Arithmetic
                7'b0001000: result = sltr; // Set Less Than
                7'b0001001: result = sltur; // Set Less Than Unsigned
                7'b0001010: result = lwr1; // Load word result 1
                7'b0001011: result = lwr2; // Load word result 2
                default: result = 32'b0; // Default to all zeros
            endcase
        end

endmodule
            
```

Operations
---

```verilog=
module not_r(y,a);
    input [31:0] a;
    output [31:0] y;
    not a0(y[0], a[0]);
    not a1(y[1], a[1]);
    not a2(y[2], a[2]);
    not a3(y[3], a[3]);
    not a0(y[4], a[4]);
    not a1(y[5], a[5]);
    not a2(y[6], a[6]);
    not a3(y[7], a[7]);
    not a0(y[8], a[8]);
    not a1(y[9], a[9]);
    not a2(y[10], a[10]);
    not a3(y[11], a[11]);
    not a0(y[12], a[12]);
    not a1(y[13], a[13]);
    not a2(y[14], a[14]);
    not a3(y[15], a[15]);
    not a0(y[16], a[16]);
    not a1(y[17], a[17]);
    not a2(y[18], a[18]);
    not a3(y[19], a[19]);
    not a0(y[20], a[20]);
    not a1(y[21], a[21]);
    not a2(y[22], a[22]);
    not a3(y[23], a[23]);
    not a0(y[24], a[24]);
    not a1(y[25], a[25]);
    not a2(y[26], a[26]);
    not a3(y[27], a[27]);
    not a0(y[28], a[28]);
    not a1(y[29], a[29]);
    not a2(y[30], a[30]);
    not a3(y[31], a[31]);
endmodule


module or_r(y,a,b);
    input [31:0] a,b;
    output [31:0] y;

or a0(y[0], a[0], b[0]);
or a1(y[1], a[1], b[1]);
or a2(y[2], a[2], b[2]);
or a3(y[3], a[3], b[3]);
or a0(y[4], a[4], b[4]);
or a1(y[5], a[5], b[5]);
or a2(y[6], a[6], b[6]);
or a3(y[7], a[7], b[7]);
or a0(y[8], a[8], b[8]);
or a1(y[9], a[9], b[9]);
or a2(y[10], a[10], b[10]);
or a3(y[11], a[11], b[11]);
or a0(y[12], a[12], b[12]);
or a1(y[13], a[13], b[13]);
or a2(y[14], a[14], b[14]);
or a3(y[15], a[15], b[15]);
or a0(y[16], a[16], b[16]);
or a1(y[17], a[17], b[17]);
or a2(y[18], a[18], b[18]);
or a3(y[19], a[19], b[19]);
or a0(y[20], a[20], b[20]);
or a1(y[21], a[21], b[21]);
or a2(y[22], a[22], b[22]);
or a3(y[23], a[23], b[23]);
or a0(y[24], a[24], b[24]);
or a1(y[25], a[25], b[25]);
or a2(y[26], a[26], b[26]);
or a3(y[27], a[27], b[27]);
or a0(y[28], a[28], b[28]);
or a1(y[29], a[29], b[29]);
or a2(y[30], a[30], b[30]);
or a3(y[31], a[31], b[31]);
endmodule


module and_r(y,a,b);
    input [31:0] a,b;
    output [31:0] y;


and a0(y[0], a[0], b[0]);
and a1(y[1], a[1], b[1]);
and a2(y[2], a[2], b[2]);
and a3(y[3], a[3], b[3]);
and a0(y[4], a[4], b[4]);
and a1(y[5], a[5], b[5]);
and a2(y[6], a[6], b[6]);
and a3(y[7], a[7], b[7]);
and a0(y[8], a[8], b[8]);
and a1(y[9], a[9], b[9]);
and a2(y[10], a[10], b[10]);
and a3(y[11], a[11], b[11]);
and a0(y[12], a[12], b[12]);
and a1(y[13], a[13], b[13]);
and a2(y[14], a[14], b[14]);
and a3(y[15], a[15], b[15]);
and a0(y[16], a[16], b[16]);
and a1(y[17], a[17], b[17]);
and a2(y[18], a[18], b[18]);
and a3(y[19], a[19], b[19]);
and a0(y[20], a[20], b[20]);
and a1(y[21], a[21], b[21]);
and a2(y[22], a[22], b[22]);
and a3(y[23], a[23], b[23]);
and a0(y[24], a[24], b[24]);
and a1(y[25], a[25], b[25]);
and a2(y[26], a[26], b[26]);
and a3(y[27], a[27], b[27]);
and a0(y[28], a[28], b[28]);
and a1(y[29], a[29], b[29]);
and a2(y[30], a[30], b[30]);
and a3(y[31], a[31], b[31]);
endmodule


module xor_r(y,a,b);
    
    input [31:0] a,b;
    output [31:0] y;
    xor a0(y[0], a[0], b[0]);
    xor a1(y[1], a[1], b[1]);
    xor a2(y[2], a[2], b[2]);
    xor a3(y[3], a[3], b[3]);
    xor a0(y[4], a[4], b[4]);
    xor a1(y[5], a[5], b[5]);
    xor a2(y[6], a[6], b[6]);
    xor a3(y[7], a[7], b[7]);
    xor a0(y[8], a[8], b[8]);
    xor a1(y[9], a[9], b[9]);
    xor a2(y[10], a[10], b[10]);
    xor a3(y[11], a[11], b[11]);
    xor a0(y[12], a[12], b[12]);
    xor a1(y[13], a[13], b[13]);
    xor a2(y[14], a[14], b[14]);
    xor a3(y[15], a[15], b[15]);
    xor a0(y[16], a[16], b[16]);
    xor a1(y[17], a[17], b[17]);
    xor a2(y[18], a[18], b[18]);
    xor a3(y[19], a[19], b[19]);
    xor a0(y[20], a[20], b[20]);
    xor a1(y[21], a[21], b[21]);
    xor a2(y[22], a[22], b[22]);
    xor a3(y[23], a[23], b[23]);
    xor a0(y[24], a[24], b[24]);
    xor a1(y[25], a[25], b[25]);
    xor a2(y[26], a[26], b[26]);
    xor a3(y[27], a[27], b[27]);
    xor a0(y[28], a[28], b[28]);
    xor a1(y[29], a[29], b[29]);
    xor a2(y[30], a[30], b[30]);
    xor a3(y[31], a[31], b[31]);
endmodule


module lw_r(
    input [31:0] rs,     
    input [31:0] offset,  
    output [31:0] y       
);
    
wire cout;
    add_r uut(y,cout,rs,offset,0);
endmodule



//ripplecarryadder
module add_r(output [31:0]sum,output c32,input [31:0]a,b,input cin);

wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c189,c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29,c30,c31;

full_adder fa0(a[0],b[0],cin,sum[0],c1);
full_adder fa1(a[1],b[1],c1,sum[1],c2);
full_adder fa2(a[2],b[2],c2,sum[2],c3);
full_adder fa3(a[3],b[3],c3,sum[3],c4);
full_adder fa4(a[4],b[4],c4,sum[4],c5);
full_adder fa5(a[5],b[5],c5,sum[5],c6);
full_adder fa6(a[6],b[6],c6,sum[6],c7);
full_adder fa7(a[7],b[7],c7,sum[7],c8);
full_adder fa8(a[8],b[8],c8,sum[8],c9);
full_adder fa9(a[9],b[9],c9,sum[9],c10);
full_adder fa10(a[10],b[10],c10,sum[10],c11);
full_adder fa11(a[11],b[11],c11,sum[11],c12);
full_adder fa12(a[12],b[12],c12,sum[12],c13);
full_adder fa13(a[13],b[13],c13,sum[13],c14);
full_adder fa14(a[14],b[14],c14,sum[14],c15);
full_adder fa15(a[15],b[15],c15,sum[15],c16);
full_adder fa16(a[16],b[16],c16,sum[16],c17);
full_adder fa17(a[17],b[17],c17,sum[17],c18);
full_adder fa18(a[18],b[18],c18,sum[18],c19);
full_adder fa19(a[19],b[19],c19,sum[19],c20);
full_adder fa20(a[20],b[20],c20,sum[20],c21);
full_adder fa21(a[21],b[21],c21,sum[21],c22);
full_adder fa22(a[22],b[22],c22,sum[22],c23);
full_adder fa23(a[23],b[23],c23,sum[23],c24);
full_adder fa24(a[24],b[24],c24,sum[24],c25);
full_adder fa25(a[25],b[25],c25,sum[25],c26);
full_adder fa26(a[26],b[26],c26,sum[26],c27);
full_adder fa27(a[27],b[27],c27,sum[27],c28);
full_adder fa28(a[28],b[28],c28,sum[28],c29);
full_adder fa29(a[29],b[29],c29,sum[29],c30);
full_adder fa30(a[30],b[30],c30,sum[30],c31);
full_adder fa31(a[31],b[31],c31,sum[31],c32);
endmodule



module sll_r (y,a,b);
    input [31:0] a,b;
    output [31:0] y;
    assign y = a << b;  // Perform left logical shift
endmodule



module srl_r (y,a,b);
    input [31:0] a,b;
    output [31:0] y;
    
    assign y = a >> b;  // Perform right logical shift
endmodule


module sra_r (
    output [31:0] y,  
    input [31:0] a,   
    input [31:0] b  
);
    assign y = a >>> b;  // Perform right arithmetic shift
endmodule


module slt_r (
    output y  
    input [31:0] a,  
    input [31:0] b,  
           
);
    assign y = (a < b) ? 1'b1 : 1'b0;  // Perform signed less than comparison
endmodule


module slt_r (
    output y,   
    input [31:0] a,  
    input [31:0] b,  
          
);
    assign y = (a < b) ? 1'b1 : 1'b0;  // Perform signed less than comparison
endmodule


module sub_r(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum,
    output c32
);
wire [31:0]w1;
not_32bit Notification(b,w1);
// Instantiate the ripple carry adder module
ripplecarryadder ripple_carry_adder_inst (
    .a(a),
    .b(w1),
    .cin(1'b1),
    .sum(sum),
    .c32(c32)
);

endmodule

module fullAdder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire s0,c1;
wire c2;
halfAdder ha0(.a(a),.b(b),.sum(s0),.cout(c1));
halfAdder ha1(.a(cin),.b(s0),.sum(sum),.cout(c2));
assign cout = c1 | c2 ;
endmodule

//halfadder

module halfAdder(a,b,sum,cout);
input a,b;
output sum,cout;
assign sum = a^ b;
assign cout = a & b;
endmodule

Processor
---

```verilog=

module processor(intstruction_mem,data_mem,reg_mem,clk,reset);
    input [31:0] instruction_mem[0:255];
    input [31:0] data_mem[0:255];
    input [31:0] reg_array[0:255];
    input clk,reset;
    
    reg [31:0] program_counter = 32'b0;
    
    Programcounter p(.clk(clk),.reset(reset),.pc(program_counter));
    
    always @(posedge clk)
        begin
           
            wire [31:0] instruction;
            instruction = instructio_mem[program_counter];
            
            wire [6:0] opcode;
            wire [4:0] destreg;
            wire [4:0] srcreg1;
            wire [4:0] srcreg2;
            wire [6:0] fun7;
            wire [11:0] imm;
            
            Instruction_decoder d(.instruction(instruction),.opcode(opcode),.destreg(destreg),.srcreg1(srcreg1),.srcreg2(srcreg2),.fun7(fun7),.imm(imm));
            
            wire [31:0] srcreg1val;
            wire [31:0] srcreg2val;
            
            Register_read r1(.reg_array(reg_array),.readreg(srcreg1),.readdata(srcreg1val));
            Register_read r2(.reg_array(reg_array),.readreg(srcreg2),.readdata(srcreg2val));
            
            wire [31:0] alu_result;
            
            alu a1(.a(srcreg1val),.b(imm),.control(opcode),.result(alu_result));
            
            if(opcode == 7'b0001011)
                begin
                    //Load
                    
                    wire [31:0] load_val;
                    Memoryread m(.address(alu_result),.read_enable(1'b1),.data_mem(data+mem),.read_data(load_val));
                    
                    Registerwrite r3(.reg_array(reg_array),.write_reg(destreg),.write_data(load_val),.write_enable(1'b1));
                end
            else if(opcode == 7'b0001100)
                begin
                    
                    Memmorywrite mw(.address(srcreg2val),.write_data(alu_result),.write_enable(1'b1),.data_mem(data_mem));
                end
            
            else
                
                begin
                    
                    Registerwrite rw(.reg_array(reg_array),.write_reg(dest_reg),.write_data(alu_result),.write_enable(1'b1));
                   
                end
        end
endmodule
                    
```


            
    
Datapath and Control
---
```verilog=
module Instructiondecoder (
    input wire [31:0] instr,  // Input: 32-bit instruction
    output reg [6:0] op,        // Output: Opcode field (7 bits)
    output reg [4:0] dest_reg,            // Output: Destination register field (5 bits)
    output reg [4:0] srcreg1,           // Output: Source register 1 field (5 bits)
    output reg [4:0] srcreg2,           // Output: Source register 2 field (5 bits)
    output reg [6:0] fun7,          // Output: Fun7 field (7 bits)
    output reg [11:0] imm     // Output: Immediate value (12 bits)
);

// Define opcode values
parameter OPCODE_LOAD = 7'b0001011;  // Opcode value for load
parameter OPCODE_STORE = 7'b0001100;  // Opcode value for store

// Decode instruction fields
always @(*) begin
    op = instr[6:0];     // Extract opcode field (bits 6-0)
    dest_reg = instr[11:7];        // Extract destination register field (bits 11-7)
    src_reg1 = instr[19:15];      // Extract source register 1 field (bits 19-15)
    src_reg2 = instr[24:20];      // Extract source register 2 field (bits 24-20)
    func_7 = instr[31:25];     // Extract func_7 field (bits 31-25)
    
    // Check if opcode is 'LOAD'
    if (op == OPCODE_LOAD) begin
        // Concatenate src_reg2 and func_7 bits to form immediate value
        imm = {srcreg2, fun7};
    end else if (op == OPCODE_STORE) begin
        // Concatenate dest_reg and func_7 bits to form immediate value
        imm = {destreg, fun7};
    end else begin
        // If opcode does not match, set immediate to 0
        imm= 12'b0;
    end
end

endmodule
```
```verilog= 
module Memorywrite (
    input [31:0] data_write,        // Data to write to memory
    input [9:0] addr,               // Address to write to in memory
    input wr_en,                    // Write enable signal
    inout [31:0] mem[0:255]         // Memory array
);
    // Write to memory if wr_en is asserted
    always @* begin
        if (wr_en) begin
            mem[addr] <= data_write;
        end
    end
endmodule

```
```verilog=
module Registerwrite (
    input [31:0] reg_file[0:31],    // Array of 32 registers
    input [4:0] write_reg_addr,     // Write address
    input [31:0] write_data,        // Data to write
    input write_enable              // Write enable signal
);
    // Write to register if write_enable is asserted
    always @* begin
        if (write_enable) begin
            reg_file[write_reg_addr] <= write_data;
        end
    end
endmodule
```
```verilog=
module Programcounter (
    input wire clk,      // Clock input
    input wire rst,      // Reset input
    output reg [31:0] pc_output  // Output: Program Counter (PC)
);

// Define the Program Counter (PC) register
reg [31:0] pc_reg;

// Increment PC on every clock cycle
always @(posedge clk or posedge rst) begin
    if (rst)
        pc_reg <= 0;  // Reset PC to initial value
    else
        pc_reg <= pc_reg + 1;  // Increment PC
end

// Output the PC value
assign pc_output = pc_reg;

endmodule

```
```verilog=
module Memoryread (
    input [9:0] addr,              // Address to read from in memory
    input rd_en,                   // Read enable signal
    input [31:0] mem[0:255],       // Memory array
    output reg [31:0] data_out     // Data read from memory
);
    // Read from memory if rd_en is asserted
    always @* begin
        if (rd_en) begin
            data_out = mem[addr];
        end
    end
endmodule

```
```verilog=
module Registerread (
    input [31:0] reg_file[0:31],    // Array of 32 registers
    input [4:0] read_reg_addr,      // Read address
    output reg [31:0] read_data     // Output data read from register
);
    // Read data from register
    always @* begin
        read_data = reg_file[read_reg_addr];
    end
endmodule
```