EESchema Usage Cheatsheet

My environment : - KiCad / EESchema version 9.0.8 - Ubuntu 24.04 LTS > Note : > SO far I just sketched high-level design of hardware components using `eeschema`, for more advanced usage such as simulation, floorplan, PCB layout, please refer to KiCad official documentation. ## File structure - schema file `.kicad_sch` must be created along with project file `.kicad_pro` - the content / syntax in schema file is completely different from previous versions. ## Paging ### Hierarchical Page - eeschema supports only hierarchical paging - one top-level diagram which collects several sub-layer diagrams - each of sub layers can be expanded to an independent electrical schematic diagram . #### Add a new hierarchical page - click `Draw Hierarchical Sheet` at right-hand toolbar of the GUI - click anywhere in current layer diagram to determine its position - GUI will prompt users to name the page and then save it to an external new file `.kicad_sch` - if the file path for `.kicad_sch` already exists , eeschema will ask to links to that existing file #### Connect Pins Across Hierarchical Page - right-click on the hierarchical page, choose `Sync Sheet Pins` - select the pins defined inside the hierarchical page , then click `Add Sheet Pins` I/O pins of each hierarchical page should be created by clicking the button `Place Hierarchical Labels` : - DO NOT use `Place Global Labels`, otherwise the pins will NOT show up for integration with other hierarchical circuits #### Resize Page To resize currnet page : - go to `file` -> `page settings` in menubar - in prompt window, set `size` to `user (custom)` then edit width and height. #### Export schematic diagram to picture - go to `file` -> `plot` in menubar - in prompt window, select `svg` or `pdf` as output format, click `plot current page` - for SVG file, use tools like [svgcleaner][6] (yes it is archived but still useful) which decreases file size by cleaning up unnecessary / invisible portions in the schema. ## Symbols for Electrical Components Any pre-defined electrical components can be added to current layer of schematic diagram, by clicking `place symbols` at right-hand toolbar, valid symbols include, but not limited to : - basic primitives, e.g. power, ground, resistor, capacitor, diode - sensors and motors e.g. for network, environment monitoring, GPS - well-known embedded deveopment boards e.g. Arduino, NodeMCU, STM32, Raspberry PI ### Create your own library for custom symbols In case KiCAD's default library does not cover your hardware design. - in menubar, go to `tools` -> `symbol editor` - a new window `symbol editor` will be launched, create your new library by clicking `new library` in menubar. - name your custom library then save it. After completed successfully, you can start adding new symbols to your custom library. - currently I only create symbols which represent high-level design of a component. - beside shapes and text, add I/O pins of the component you are editing , by clicking `Draw Pins` on right-hand side toolbar. ## SPICE Simulation This section describes minimal required tasks which have to be done before you actually run simulation - [SPICE relevant background knowledge][9] ### Seperate Simulation From Production Design As of KiCAD v9.0.8 , an eeschema project `.kicad_sch` is unable to select partial circuit in a hierarchical sheet, or even specify one of the sheets for simulation. - [SPICE simulation for individual hierarchical sheets][10] - [KiCAD GitLab issue 6329, Simulate subsheets only][11], 6-year-old issue and still working in progress Current workaround is to create separate project ONLY for simulation purpose , and link to the production circuit you'd like to test. For example : - place core circuit design `soil sensor` to `soil-sensor.kicad_sch` - in another application circuit `my-app-123.kicad_sch`, draw a hierarchical sheet which links to existing `soil-sensor.kicad_sch` . - for simulation, build a separate project `soil-sensor-sim.kicad_sch` , draw a hierarchical sheet which links to the `soil-sensor.kicad_sch` . ### Power Source Simulation Model add following symbols for SPICE circuit simulation (by searching `spice` in `choose symbol` prompt window) : - `VDC` , then modify target DC or AC voltage parameters. - ground / 0V reference (labeled `0`) ### Map IC Symbols to SPICE model In eeschema , almost all symbols requires corresponding SPICE models for smooth simulation. - double-click the symbol --> open `simulation model editor` in `symbol properties` prompt window. - SPICE models can be imported from either external file or built-in one Simple components like resistors or capacitors don't have many complex electrical characteristics, you can simply configure them with built-in SPICE model. For IC (Integrated-Circuit) components like op-amps, MOSFET, timers , it'd be good to manage all the complex electrical characteristics, to external SPICE model file , depending on how much detail you need for a simulation run. - one single external file could have several models definition - once imported from external file, **map the pins of the eeschema symbol, to pis of the chosen SPICE model** , this step can be done in `pin assignments` tab of `simulation model editor` prompt window under each symbol property. > [CAUTION] > --- > Huge part of efficient / accurate simulation heavily relies on correctness of the SPICE models . **Unfortunately** , many of manufacturers might NOT provide them : > - it is **RARE** to find open-sourced ones, but there are few model examples from online forums. > - **avoid scammy / malicious sites which pretend to provide the models** > > To build it from scratch you need extremely deep knowledge about the electrical characteristics of each component, that is beyond the scope of this note. ### Embed Variables to Components (incomplete) - add `{Cvar}` to simulation model of a component (e.g. ressitor, capacitor, diode ... etc.) - it helps to specify different value for each simulation ### Plot Waveform on Display Panel (incomplete) TODO, figure out why the plotted wave from probe points are not stable. ## Reference - [KiCad 9.0 EESchema Reference Manual][1] - [explain the power flag - KiCad subreddit][2] - [ERC error: Input power pin not driven by output power pins -- KiCad official forum][3] - [Hide power flag when printing -- use it as helper rather than ERC satisfication][4] - [Best practice for unused pins -- EE stackexchange][5] - [Guide to Transient Analysis in SPICE Simulations for Electronics -- Altium][7] - [resize schematic page -- official forum][8] - [Tutorial ngspice simulation in KiCAD / Eeschema][12] [1]: https://docs.kicad.org/9.0/en/eeschema/eeschema.html [2]: https://www.reddit.com/r/KiCad/comments/lwnof0/ [3]: https://forum.kicad.info/t/erc-error-input-power-pin-not-driven-by-output-power-pins/35552 [4]: https://forum.kicad.info/t/hide-pwr-flag-when-printing/15107/7 [5]: https://electronics.stackexchange.com/a/730078/549311 [6]: https://github.com/RazrFalcon/svgcleaner [7]: https://resources.altium.com/p/guide-transient-analysis-spice-simulations-electronics [8]: https://forum.kicad.info/t/resize-schematic/24937/2 [9]: https://hackmd.io/@0V3cv8JJRnuK3jMwbJ-EeA/SJ8QEmanZg [10]: https://forum.kicad.info/t/spice-simulation-for-individual-hierarchical-sheets/43068 [11]: https://gitlab.com/kicad/code/kicad/-/work_items/6329 [12]: https://ngspice.sourceforge.io/ngspice-eeschema.html#setting ###### tags: `Electronic Design`