--- # System prepended metadata title: Chap 15 Reduction of State Tables State Assignment tags: [SCLD] --- --- ###### tags: `SCLD` --- # Chap 15 Reduction of State Tables State Assignment ## 15.1 Elimination of Redundant States example from [14.3](https://hackmd.io/LXOP-VITQvud6TBSDE25uA?both#143-Guidelines-for-Construction-of-State-Graphs) The circuit examines groups of four consecutive inputs and produces an output Z = 1 if the input sequence 0101 or 1001 occurs. The circuit resets after every four inputs. 4 bit → reset → A ![](https://i.imgur.com/K7zy37c.png) H → next state A, output 0 I → next state A, output 0 so eliminate I ![](https://i.imgur.com/h6Umirs.png) ![](https://i.imgur.com/8qx8FEt.png) 畫出同 14.3 的圖 ![](https://i.imgur.com/rmVJHRY.png) ## 15.2 Equivalent States ![](https://i.imgur.com/0lJ4501.png) ![](https://i.imgur.com/bmPgFI0.png) ## 15.3 Determination of State Equivalence Using an Implication Table example ![](https://i.imgur.com/RIVYN7K.png) x & y 相等的條件 ![](https://i.imgur.com/PX8Q5Eu.png) 不可能 → 打叉 多餘的 → 劃掉 (d,f) 打叉 → (a,b)不可能 → (a,b) 打叉 ![](https://i.imgur.com/Wjtaf9J.png) 一樣 ![](https://i.imgur.com/zHIJzZD.png) ## 15.4 Equivalent Sequential Circuits ![](https://i.imgur.com/CFvCHkO.png) 兩張圖比較，做 implication table ![](https://i.imgur.com/lFsv0af.png) ## Problems #### 15.10(b) ![](https://i.imgur.com/EFFZoQT.png) ans ![](https://i.imgur.com/KI6v7EW.png) #### 15.11(b) ![](https://i.imgur.com/bSnB5Hx.png) ans ![](https://i.imgur.com/F0hvlaw.png) #### 15.12 ![](https://i.imgur.com/AD6A41H.png) ![](https://i.imgur.com/CmuGjAQ.png) ans ![](https://i.imgur.com/Yb572KC.png) ![](https://i.imgur.com/e0Tuyop.png) ![](https://i.imgur.com/ScyISdW.png) #### 15.17 ![](https://i.imgur.com/md7Hfhf.png) ans ![](https://i.imgur.com/krF65AR.png) ![](https://i.imgur.com/9TOErDL.png) #### 15.35 這 15.9 的 不會考 ![](https://i.imgur.com/b9PBrME.png) ans ![](https://i.imgur.com/Axm3gEn.png) #### 15.40 ![](https://i.imgur.com/GupfiXu.png) ans ![](https://i.imgur.com/kHBBQq8.png)