---
# System prepended metadata

title: LC 08 (2021) - zad 5

---

# LC 08 (2021) - zad 5

```verilog
module circuit(
  input [15:0] a,
  input [15:0] b,
  input clk,
  input load,
  output logic [15:0] r,
  output rdy
);
  logic [15:0] reg_a;
  logic [15:0] reg_b;

  always_ff @(posedge clk)
    if (load) begin
      reg_a <= a
      reg_b <= b
    end else if (!rdy)
      if (reg_b > reg_a) begin
        reg_a <= reg_b
        reg_b <= reg_a
      end else begin
        reg_a <= reg_a - reg_b
      end
    end
  
  assign r = reg_a | reg_b;
  assign rdy = !|reg_a || !|reg_b;
endmodule
```

```verilog
module circuit(
  input [15:0] a,
  input [15:0] b,
  input clk,
  input load,
  output logic [15:0] r,
  output rdy
);
  logic [15:0] reg_a;
  logic [15:0] reg_b;
  always_ff @(posedge clk)
    if (load) begin
      reg_a <= a;
      reg_b <= b;
    end else if (!rdy)
      if (reg_b > reg_a) begin
        reg_a <= reg_b;
        reg_b <= reg_a;
      end else begin
        reg_a <= reg_a - reg_b;
      end
  assign r = reg_a | reg_b;
  assign rdy = !|reg_a || !|reg_b;
endmodule
```