---
# System prepended metadata

title: Lab 2 Report

---

# Lab 2 Report

Group members:
-	Xuyang Zhou (nickzhouxy@g.ucla.edu)
-	Peicheng (Mike) Shi (mikespc@g.ucla.edu)
-	Chang Xu (changx28@g.ucla.edu) 


## Introduction
There are hundreds of ways to represent numbers. An unique one of them is using a floating-point representation. In a floating point representation, numbers will be converted into a binary array where the first bit will represent the sign of the number $S$ (0 for positive, 1 for negative). For an 8 bit floating-point representation, the next 3 bit will contain the exponent $E$ value, whereas the last 4 bit will contain the significand $F$ of the number representation. The total representation is computed as $S\times(2^E)\times F$. Any input numbers will be represented by the closest representation that exist. Our goal in this mission is to create a verilog project that takes in a 12 bit binary input and output its floating-point representation with the sign bit $S$, exponent $E$, and significand $F$ seperately.
 
## Our Design
Our design has 4 modules: `sign`, `extract`, `rounding`, and `fpcv`. `fpcv` is responsible for the overall function and will call the three other modules. `sign`, `extract`, and `rounding` are helper functions to implement different steps throughout the coverting process.

### `sign` Module
The first part of this lab is to simply extract the sign bit of the input string, which we used the `sign` module to do that.
Going through our code, we only have to put an `if` statement checking `D[11]` where `D` is the input string. If `D[11]==1`, then we know the sign bit is `1` and we have to output the negate of the original input `~D`; otherwise we know the sign bit is `0`, and we do nothing to `D`.

### `extract` Module
Taking in the 12 bit output of the `sign` module, we first find the position first bit from most significand to least. Then, we compute our exponent $E$ accordingly to the numbers of leading 0 reflected by the first leading 1. If there are $n$ leading 0s, $E$ should have decimal value of 8-n. Then we extract the first four digits starting with the leading one and output it as our current significands without rounding. The fifth digit of the input will also be output singularly as a flag for rounding or not. 

Thus, taking the 12 bit input from sign module, the extract module will extract the unrounded exponents, signidicands, and the rounding flag and pass them into the rounding module to be rounded accordingly.

**Edge case handling**: The above heuristic is applicable for most input scenarios but there exist edge cases. When the input is negative maximum, which is the only circumstance where the input to extract module will have a leading 1 instead of a leading 0, the exponent and significand will be directly assigned as all 1s with the rounding flag set as 1 as well.

### `rounding` Module
The `rounding` model takes the outputs of `extract` and rounds the output to the clostest floating point representation. If the fifth bit is 0, no rounding is required. Then the output exponent and significand are the same as input. 

When the fifth bit is 1, we first check if significand overflows when added by 1. If not, we add it by 1 and return. If overflow will occur, we then check if exponent overflows when added by 1. If so, we know that the input is greater than the maximum floating point we can represent, and we just output the greatest floating point representation. Otherwise, we set significand to `1000`, increment exponent by 1, and return. 

Finally, the `rounding` module outputs the rounded significand and exponent to `fpcv` module. 


### `fpcv` Module
This is the main function of this lab, in which we will call the aforementioned helper functions. 
We first call the `sign` module, and will get a resulting sign bit and converted output `D` (negated or original depending on the sign bit). With the converted `D`, we then pass it into the `extract` module, from which we will get the unrounded exponents, signidicands, and the rounding flag. These will be used as inputs to the `rounding` module, from which we will get the final result of the rounded significand and exponent. Combining all of that, the `fpcv` module will output the sign bit, rounded significand, and exponent as desired.


## Simulation

We did simulations on all sub-modules excepting `fpcv` before integrating them together. During the process, example inputs in the lab documentation are taken as test cases for each module. Finally, after we finished the `fpcv` module, a set of test cases covering edge cases are tested on our overall design.

A bug we discovered during testing is that the `extract` module fails to handle the most negative input: `-2048`. It was handled as mentioned in the edge case part in the [`extract` module description](#extract-Module). 


Our test cases are:
```verilog=
// D is the input variable to fpcv module
#100;
D = 0;
#100;
D = 2047;
#100;
D = -2048;
#100;
D = -693;
#100;
D = 6;
#100;
D = 79;
#100;
D = 1835;
#100;
D = -1001;
#100;
D = 239;
#100;
D = 1001;
#100;
$finish;	
```

The waveform of of the test cases is (D is the input, S is the sign bit, E is the exponent, F is the significand):
![](https://i.imgur.com/LogNXPn.png)




## Conclusion
Through this lab, we deepened our understanding of verilog and bit manipulation. One major difficulty we met is the usage of loop in this lab, since we were not familiar with verilog grammar and conventions. We resolve the problem through a more brute force manual check. One suggestion for this lab in the future may be helping students to understand more on verilog loops through this lab.



