---
# System prepended metadata

title: 'SMP WG, January 24, 2023'
tags: [' synchronization', ' smp', unikraft]

---

---
title: "SMP WG, January 24, 2023"
tags: unikraft, smp, synchronization
datetime: 2023-01-24T15:30:00+02:00
location: Online, Discord (https://bit.ly/UnikraftDiscord), the `#monkey-business` voice channel
teams:
- smp
participants:
- TODO
---

## :dart: Agenda

- Status update
- Next steps

## :closed_book: Discussions

### ISR-safe

AS: I'm using a shared-object and I use a callback when a function is parsed.

AS: The nodes in the AST have different structures.
I was unable to find all the child nodes.
So I need to use accessors for each type of node.

AS: I looked for using object tool.
I was trying to place the ISR into a separate section.

MR: Isn't there an attribute that you can specify for a function to no use these registers?
Or something with a `#pragma`?

MR: There is an enum for `plugin_event`.
There a `finish_function`.

MR: There is an enum named `plugin_attribute`.

### Synchronization

SjK: I rebased the synchronization PR.

SjK: It broke my read-write lock implementation.

When I configure the interrupt destination, and the interrupts are not delivered.

I took a look on how `virtio` would work with SMP.

How should I use synchronization?
At device level, at PCI level.

MR: If you have multiple core and one device, what components would you share between the cores.

Maybe you wouldn't need to synchronize at queue-level, but you would need to synchronize at PCI-level.

Maybe the next step would be to draw a picture and see what components are involved.

MR: If you can configure CPU dedicated queues and then you can remove

SjK: The synchronization PRs are reviewed.
The IOAPIC issue still persists.

AP: What is the testing setup / scenario?

SjK: I'm running multiple functions on multiple core.

SjK: It would be useful to involve some 

MR: Maybe you could just do some `uktest` and do multiple tests to check the synchronization work.

## :wrench: TODOs and Decisions

TODO